altera Nios V Embedded Processor User Guide

Awọn akoonu tọju

1 altera Nios V Ifibọ Prosessor

2 Awọn pato

3 Nios V Prosessor Hardware System Design

4 Nios V Prosessor Software System Design

5 Nios V isise iṣeto ni ati Booting Solusan

altera Nios V Embedded Processor User Guide

altera Nios V Ifibọ Prosessor

Awọn pato

Orukọ ọja: Nios V Processor
Ibamu Software: Quartus Prime Software ati Platform Designer
Isise Iru: Altera FPGA
Memory System: Iyipada ati Non-iyipada Memory
Interface ibaraẹnisọrọ: UART Aṣoju

Nios V Prosessor Hardware System Design

Lati ṣe apẹrẹ ẹrọ ohun elo Nios V Processor, tẹle awọn igbesẹ wọnyi:

Ṣẹda Nios V Processor eto apẹrẹ lilo Platform onise.
Ṣepọ eto naa sinu iṣẹ akanṣe Quartus Prime.
Eto iranti oniru pẹlu iyipada ati iranti ti kii ṣe iyipada.
Ṣiṣe awọn aago ati tunto awọn iṣe ti o dara julọ.
Fi aiyipada ati awọn aṣoju UART fun iṣẹ ṣiṣe daradara.

Nios V Prosessor Software System Design

Lati ṣe apẹrẹ eto sọfitiwia fun Nios V Processor:

Tẹle ṣiṣan idagbasoke sọfitiwia fun Nios V Processor.
Ṣẹda Board Support Package Project ati Ohun elo Project.

Nios V isise iṣeto ni ati Booting Solusan

Fun atunto ati booting ni Nios V Processor:

Loye ifihan si iṣeto ni ati awọn solusan bata.
Awọn ohun elo ọna asopọ fun iṣẹ-ṣiṣe lainidi.

Nipa Nios® V isise ifibọ
1.1. Altera® FPGA ati Ifibọ Processors Loriview
Awọn ẹrọ Altera FPGA le ṣe imuse ọgbọn ti o ṣiṣẹ bi microprocessor pipe lakoko ti o pese ọpọlọpọ awọn aṣayan.
Iyatọ pataki laarin awọn microprocessors ọtọtọ ati Altera FPGA ni pe aṣọ Altera FPGA ko ni imọran nigba ti o ni agbara. Nios® V ero isise jẹ ohun-ini imọ-jinlẹ rirọ (IP) ti o da lori sipesifikesonu RISC-V. Ṣaaju ki o to ṣiṣẹ sọfitiwia lori eto orisun ero isise Nios V, o gbọdọ tunto ẹrọ Altera FPGA pẹlu apẹrẹ ohun elo ti o ni ero isise Nios V kan. O le gbe ero isise Nios V nibikibi lori Altera FPGA, da lori awọn ibeere ti apẹrẹ naa.

Lati jẹ ki eto ifibọ IP ti Altera® FPGA rẹ ṣe lati huwa bi eto orisun microprocessor ọtọtọ, eto rẹ yẹ ki o pẹlu atẹle naa: · AJTAG ni wiwo lati ṣe atilẹyin iṣeto Altera FPGA, hardware ati sọfitiwia
n ṣatunṣe aṣiṣe · Ilana iṣeto ni Altera FPGA agbara
Ti eto rẹ ba ni awọn agbara wọnyi, o le bẹrẹ isọdọtun apẹrẹ rẹ lati inu apẹrẹ ohun elo ti a ti yan tẹlẹ ti kojọpọ ni Altera FPGA. Lilo Altera FPGA tun ngbanilaaye lati yipada apẹrẹ rẹ ni kiakia lati koju awọn iṣoro tabi lati ṣafikun iṣẹ ṣiṣe tuntun. O le ṣe idanwo awọn apẹrẹ ohun elo tuntun wọnyi ni irọrun nipa atunto Altera FPGA ni lilo JTAG ni wiwo.
Awọn JTAG ni wiwo atilẹyin hardware ati software idagbasoke. O le ṣe awọn iṣẹ ṣiṣe wọnyi nipa lilo JTAG ni wiwo: · Tunto Altera FPGA · Ṣe igbasilẹ ati yokokoro sọfitiwia · Ibasọrọ pẹlu Altera FPGA nipasẹ wiwo UART kan (J)TAG UART
ebute) · Ohun elo yokokoro (pẹlu Oluyanju ọgbọn ti a fi sii ifihan agbara) · Iranti filasi eto
Lẹhin ti o tunto Altera FPGA pẹlu apẹrẹ ti o da lori ero isise Nios V, ṣiṣan idagbasoke sọfitiwia jọra si sisan fun awọn apẹrẹ microcontroller ọtọtọ.

Jẹmọ Alaye · AN 985: Nios V isise Tutorial
Itọsọna ibẹrẹ iyara kan nipa ṣiṣẹda eto ero isise Nios V ti o rọrun ati ṣiṣe ohun elo Hello World.
© Altera Corporation. Altera, aami Altera, aami 'a', ati awọn ami Altera miiran jẹ aami-iṣowo ti Altera Corporation. Altera ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Altera ko gba ojuse tabi layabiliti ti o waye lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Altera. A gba awọn alabara Altera nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

1. Nipa Nios® V Ifibọ isise 726952 | 2025.07.16
· Nios V Ilana Itọkasi Itọkasi Pese alaye nipa awọn aṣepari iṣẹ ero isise Nios V, faaji ero isise, awoṣe siseto, ati imuse mojuto.
Itọnisọna Olumulo IP Awọn agbeegbe ti a fi sinu · Nios V Processor Software Handbook

Ṣe apejuwe agbegbe idagbasoke sọfitiwia ero isise Nios V, awọn irinṣẹ ti o wa, ati ilana lati kọ sọfitiwia lati ṣiṣẹ lori ero isise Nios V. · Ashling * RiscFree * Integrated Development Environment (IDE) fun Altera FPGAs olumulo Itọsọna Apejuwe RiscFree * ese idagbasoke ayika (IDE) fun Altera FPGAs Arm * -orisun HPS ati Nios V mojuto ero isise. · Nios V Prosessor Altera FPGA IP Awọn akọsilẹ Tu
1.2. Quartus® Prime Software Support
Nios V isise Kọ sisan ti o yatọ si fun Quartus® Prime Pro Edition software ati Quartus Prime Standard Edition software. Tọkasi AN 980: Nios V Processor Quartus Prime Software Atilẹyin fun alaye diẹ sii nipa awọn iyatọ.
Alaye ti o jọmọ AN 980: Nios V Processor Quartus Prime Software Support
1.3. Nios V isise iwe-aṣẹ
Iyatọ ero isise Nios V kọọkan ni bọtini iwe-aṣẹ rẹ. Ni kete ti o ba gba bọtini iwe-aṣẹ, o le lo bọtini iwe-aṣẹ kanna fun gbogbo awọn iṣẹ ero isise Nios V titi di ọjọ ipari. O le gba Nios V Processor Altera FPGA IP awọn iwe-aṣẹ ni idiyele odo.
Akojọ bọtini iwe-aṣẹ ero isise Nios V wa ni Ile-iṣẹ Iwe-aṣẹ Iṣẹ-ara Altera FPGA. Tẹ Forukọsilẹ fun Igbelewọn tabi taabu Iwe-aṣẹ Ọfẹ, ki o yan awọn aṣayan ti o baamu lati ṣe ibeere naa.
olusin 1. Ile-iṣẹ Gbigbanilaaye Iṣẹ-ara-ara Altera FPGA

Pẹlu awọn bọtini iwe-aṣẹ, o le:
Fi esi ranṣẹ

Nios® V Iwe amudani Oniru ero isise 7

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Ṣe imuse ero isise Nios V laarin eto rẹ. Ṣe afiwe ihuwasi ti eto ero isise Nios V kan. · Daju iṣẹ ṣiṣe ti apẹrẹ, bii iwọn ati iyara. · Ina ẹrọ siseto files. · Ṣe eto ẹrọ kan ati rii daju apẹrẹ ni ohun elo.
Iwọ ko nilo iwe-aṣẹ lati ṣe agbekalẹ sọfitiwia ni Ashling * RiscFree * IDE fun Altera FPGAs.
Alaye ti o jọmọ · Ile-iṣẹ Iwe-aṣẹ Iṣẹ-ara-ẹni Altera FPGA
Fun alaye diẹ sii nipa gbigba Nios V Processor Altera FPGA awọn bọtini iwe-aṣẹ IP. Fifi sori ẹrọ Software Altera FPGA ati Iwe-aṣẹ Fun alaye diẹ ẹ sii nipa gbigba iwe-aṣẹ sọfitiwia Altera FPGA ati ṣeto iwe-aṣẹ ti o wa titi ati olupin iwe-aṣẹ nẹtiwọọki.
1.4. Ifibọ System Design
Nọmba ti o tẹle n ṣapejuwe ṣiṣan ero ero isise Nios V ti o rọrun, pẹlu ohun elo mejeeji ati idagbasoke sọfitiwia.

Nios® V Iwe amudani Oniru ero isise 8

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Olusin 2.

Nios V Prosessor System Sisan
Eto Erongba

Itupalẹ System ibeere

Nios® V
Awọn ohun kohun isise ati Standard irinše

Setumo ati ina System ni
Platform onise

Sisan Hardware: Ṣepọ ati Ṣajọ Intel Quartus Prime Project

Ṣiṣan sọfitiwia: Dagbasoke ati Kọ sọfitiwia igbero Nios V

Sisan Hardware: Ṣe igbasilẹ Apẹrẹ FPGA
to Àkọlé Board

Ṣiṣan sọfitiwia: Idanwo ati Ṣatunkọ Nios V Software Processor

Software Ko si Pade Spec?
Bẹẹni
Hardware Ko Pade Spec? Bẹẹni
Eto Pari

Fi esi ranṣẹ

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Olusin 3.

Aworan atọka atẹle yii ṣe afihan apẹrẹ ohun elo ero isise Nios V aṣoju kan. Nios V Prosessor System Hardware Design Sisan

Bẹrẹ

Nios V ohun kohun ati Standard irinše

Lo Apẹrẹ Platform lati ṣe apẹrẹ Eto Ipilẹ Nios V kan
Ina Platform onise Design

Ṣepọpọ Platform Designer System pẹlu Intel Quartus Prime Project
Fi Awọn ipo Pin, Awọn ibeere akoko, ati Awọn ihamọ Oniru miiran
Ṣe akopọ Hardware fun Ẹrọ Àkọlé ni Intel Quartus Prime

Setan lati gba lati ayelujara
2.1. Ṣiṣẹda Nios V Processor System Design with Platform Designer
Sọfitiwia Prime Quartus pẹlu ohun elo isọpọ ẹrọ Apẹrẹ Platform ti o rọrun iṣẹ-ṣiṣe ti asọye ati sisọpọ Nios V ero isise IP core ati awọn IPs miiran sinu apẹrẹ eto Altera FPGA. Oluṣeto Platform laifọwọyi ṣẹda imọ-ọrọ interconnect lati ipo asopọ giga ti pàtó kan. Adaṣiṣẹpọ interconnect ṣe imukuro iṣẹ-ṣiṣe ti n gba akoko ti sisọ awọn asopọ HDL ipele eto.
© Altera Corporation. Altera, aami Altera, aami 'a', ati awọn ami Altera miiran jẹ aami-iṣowo ti Altera Corporation. Altera ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Altera ko gba ojuse tabi layabiliti ti o waye lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Altera. A gba awọn alabara Altera nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

2. Nios V Processor Hardware System Design pẹlu Quartus Prime Software ati Platform Designer
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Lẹhin ti n ṣatupalẹ awọn ibeere ohun elo eto, o lo Quartus Prime lati ṣalaye ipilẹ ero isise Nios V, iranti, ati awọn paati miiran ti eto rẹ nilo. Oluṣeto Platform laifọwọyi n ṣe agbekalẹ kannaa isọpọ lati ṣepọ awọn paati ninu eto ohun elo.

2.1.1. Instantiating Nios V Prosessor Altera FPGA IP

O le ṣe imudara eyikeyi awọn ohun kohun IP ero isise ni Platform Designer IP Catalog Processors ati Awọn ilana ifibọ Agbeegbe.

Ipilẹ IP ti ero isise kọọkan ṣe atilẹyin awọn aṣayan iṣeto oriṣiriṣi ti o da lori faaji alailẹgbẹ rẹ. O le ṣalaye awọn atunto wọnyi lati baamu awọn iwulo apẹrẹ rẹ dara julọ.

Tabili 1.

Awọn aṣayan Iṣeto ni Kọja Awọn iyatọ Core

Awọn aṣayan iṣeto ni

Nios V/c isise

Nios V / m isise

Ṣatunkọ Lo Ibeere Tunto

Ẹgẹ, Awọn imukuro, ati Idilọwọ

Sipiyu Architecture

ECC

Awọn caches, Awọn agbegbe agbeegbe ati awọn TCM

Aṣa Ilana

Igbesẹ titiipa

Nios V/g isise

2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Figure 4. Nios V/c Compact Microcontroller Altera FPGA IP

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2.1.1.1.1. Sipiyu Architecture Tab

Tabili 2.

Sipiyu Architecture Tab

Ẹya ara ẹrọ

Apejuwe

Mu Avalon® Interface ṣiṣẹ Mu Interface Avalon ṣiṣẹ fun oluṣakoso itọnisọna ati oluṣakoso data. Ti o ba jẹ alaabo, eto naa nlo wiwo AXI4-Lite.

mhartid CSR iye

· Aṣayan IP ti ko tọ. · Ma ṣe lo mhartid CSR iye ni Nios V/c isise.

2.1.1.1.2. Lo Taabu Ibere Tunto

Tabili 3.

Lo Ibere Ibere Taabu Paramita

Lo Taabu Ibere Tunto

Apejuwe

Fi Atunto Ibere ni wiwo

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· Ifihan agbara resetreq gbọdọ wa ni idaniloju titi ti ero isise yoo fi sọ ifihan agbara ack. Ikuna fun ifihan agbara lati wa ni idaniloju le fa ki ero isise wa ni ipo ti kii ṣe ipinnu.
· Oluṣeto Nios V ṣe idahun pe atunto naa ṣaṣeyọri nipasẹ sisọ ifihan agbara ack.
· Lẹhin ti awọn isise ti wa ni ifijišẹ tun, awọn itenumo ti awọn ack ifihan agbara le ṣẹlẹ ọpọ igba lorekore titi de-itẹnumọ ti awọn resetreq ifihan agbara.

2.1.1.1.3. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 4.

Ẹgẹ, Awọn imukuro, ati Idilọwọ Awọn paramita Taabu

Ẹgẹ, Awọn imukuro, ati Idilọwọ

Apejuwe

Aṣoju atunto

Tun aiṣedeede

· Sọ aiṣedeede ti fekito atunto ojulumo si adirẹsi ipilẹ oluranlowo ti o yan. · Platform onise laifọwọyi pese a aiyipada iye fun awọn ipilẹ aiṣedeede.

Akiyesi:

Apẹrẹ Platform n pese aṣayan pipe, eyiti o fun ọ laaye lati pato adirẹsi pipe ni Tunto Aiṣedeede. Lo yi aṣayan nigbati awọn iranti titoju fekito atunto ti wa ni be ni ita ero isise eto ati subsystems.

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2.1.1.1.4. ECC Taabu

Tabili 5.

ECC Taabu

ECC

Jeki Wiwa aṣiṣe ati Ijabọ Ipo

Apejuwe
· Mu aṣayan yii ṣiṣẹ lati lo ẹya ECC fun awọn bulọọki Ramu inu ero isise Nios V. Awọn ẹya ECC ṣe awari to awọn aṣiṣe 2-bits ati fesi da lori ihuwasi atẹle:
- Ti o ba jẹ aṣiṣe atunṣe 1-bit, ero isise naa tẹsiwaju lati ṣiṣẹ lẹhin atunṣe aṣiṣe ninu opo gigun ti ẹrọ. Sibẹsibẹ, atunṣe ko han ninu awọn iranti orisun.
- Ti aṣiṣe naa ko ba ṣe atunṣe, ero isise naa tẹsiwaju lati ṣiṣẹ laisi atunṣe ni opo gigun ti epo ati awọn iranti orisun, eyiti o le fa ki ero isise naa tẹ ipo ti kii ṣe ipinnu.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Figure 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. yokokoro Taabu

Tabili 6.

yokokoro Tab paramita

yokokoro Taabu

Apejuwe

Mu yokokoro ṣiṣẹ
Jeki Tunto lati Module yokokoro

Mu aṣayan yii ṣiṣẹ lati ṣafikun JTAG module asopọ afojusun si ero isise Nios V. · Awọn JTAG afojusun asopọ module faye gba pọ si awọn Nios V isise nipasẹ awọn
JTAG ni wiwo pinni ti FPGA. · Asopọ naa pese awọn agbara ipilẹ wọnyi:
- Bẹrẹ ati da ero isise Nios V duro - Ṣayẹwo ati ṣatunkọ awọn iforukọsilẹ ati iranti. - Ṣe igbasilẹ ohun elo Nios V .elf file si iranti isise ni asiko isise nipasẹ
niosv-gbigba. - Ṣatunkọ ohun elo ti n ṣiṣẹ lori ero isise Nios V · So dm_agent ibudo si itọnisọna ero isise ati ọkọ ayọkẹlẹ data. Rii daju pe adirẹsi ipilẹ laarin awọn ọkọ akero mejeeji jẹ kanna.
Mu aṣayan yii ṣiṣẹ lati ṣipaya dbg_reset_out ati awọn ibudo ndm_reset_in. · JTAG debugger tabi aṣẹ niosv-download -r nfa dbg_reset_out, eyiti
ngbanilaaye ero isise Nios V lati tun awọn agbeegbe eto ti o sopọ si ibudo yii. O gbọdọ so dbg_reset_out ni wiwo si ndm_reset_in dipo atunto
ni wiwo lati ma nfa si ipilẹ to ero isise mojuto ati aago module. O ko gbodo so dbg_reset_out ni wiwo lati tun ni wiwo lati se idinamọ iwa.

2.1.1.2.2. Lo Taabu Ibere Tunto

Tabili 7.

Lo Ibere Ibere Taabu Paramita

Lo Taabu Ibere Tunto

Apejuwe

Fi Atunto Ibere ni wiwo

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· Ifihan agbara resetreq gbọdọ wa ni idaniloju titi ti ero isise yoo fi sọ ifihan agbara ack. Ikuna fun ifihan agbara lati wa ni idaniloju le fa ki ero isise wa ni ipo ti kii ṣe ipinnu.
· Imudaniloju ifihan agbara restreq ni ipo yokokoro ko ni ipa lori ipo ero isise naa.
· Oluṣeto Nios V ṣe idahun pe atunto naa ṣaṣeyọri nipasẹ sisọ ifihan agbara ack.
· Lẹhin ti awọn isise ti wa ni ifijišẹ tun, awọn itenumo ti awọn ack ifihan agbara le ṣẹlẹ ọpọ igba lorekore titi de-itẹnumọ ti awọn resetreq ifihan agbara.

2.1.1.2.3. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 8.

Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Apejuwe

Aṣoju atunto

Ipo Idilọwọ aiṣedeede tunto

· Sọ aiṣedeede ti fekito atunto ojulumo si adirẹsi ipilẹ oluranlowo ti o yan. · Platform onise laifọwọyi pese a aiyipada iye fun awọn ipilẹ aiṣedeede.
Pato iru oludari idalọwọduro boya Taara tabi Vectored. Akiyesi: Nios V/m ero isise ti kii-pipelin ko ṣe atilẹyin awọn idilọwọ Vectored.
Nitorinaa, yago fun lilo ipo idalọwọduro Vectored nigbati ero isise ba wa ni ipo Nonpipelined.

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Akiyesi:

2.1.1.2.4. Sipiyu Architecture

Tabili 9.

Sipiyu Architecture Tab paramita

Sipiyu Architecture

Apejuwe

Mu Pipelining ṣiṣẹ ni Sipiyu

Mu aṣayan yii ṣiṣẹ lati mu ẹrọ isise Nios V/m pipelined lẹsẹkẹsẹ. - IPC ga julọ ni idiyele ti agbegbe kannaa ti o ga ati igbohunsafẹfẹ Fmax kekere.
Mu aṣayan yii ṣiṣẹ lati mu ẹrọ isise Nios V/m ti kii ṣe opo pọ si. - Ni iṣẹ mojuto iru bi ero isise Nios V/c. - Atilẹyin n ṣatunṣe aṣiṣe ati da gbigbi agbara - Agbegbe oye kekere ati igbohunsafẹfẹ Fmax ti o ga julọ ni idiyele ti IPC kekere.

Mu Avalon Interface ṣiṣẹ

Mu Avalon Interface ṣiṣẹ fun oluṣakoso itọnisọna ati oluṣakoso data. Ti o ba jẹ alaabo, eto naa nlo wiwo AXI4-Lite.

mhartid CSR iye

· Hart ID Forukọsilẹ (mhartid) iye 0 ni aiyipada. · Fi iye kan laarin 0 ati 4094. · Ni ibamu pẹlu Altera FPGA Avalon Mutex Core HAL API.

Alaye ti o jọmọ Ifibọ Agbeegbe IP Itọsọna olumulo – Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Taabu
Table 10. ECC Tab
ECC Mu Wiwa aṣiṣe ṣiṣẹ ati Ijabọ Ipo

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2.1.1.3. Instantiating Nios V/g Gbogbogbo Idi isise Altera FPGA IP
Nọmba 6. Nios V/g Oluṣeto Idi Gbogbogbo Altera FPGA IP – Apakan 1

Olusin 7.

Nios V/g Olupilẹṣẹ Idi Gbogbogbo Altera FPGA IP – Apakan 2 (Pa a Muu Adari Idilọwọ Ipele Core ṣiṣẹ)

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Olusin 8.

Nios V/g Olupilẹṣẹ Idi Gbogbogbo Altera FPGA IP – Apá 2 (Ṣi-an Muu Adari Idilọwọ Ipele Core ṣiṣẹ)

Nọmba 9. Nios V/g Oluṣeto Idi Gbogbogbo Altera FPGA IP – Apakan 3

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Nọmba 10. Nios V/g Oluṣeto Idi Gbogbogbo Altera FPGA IP – Apakan 4

2.1.1.3.1. Sipiyu Architecture

Table 11. Sipiyu Architecture Parameters

CPU Architecture Tab Mu Lilefoofo Point Unit

Apejuwe Mu aṣayan yii ṣiṣẹ lati ṣafikun ẹyọ-ojuami lilefoofo (“F” itẹsiwaju) ninu mojuto ero isise.

Mu Asọtẹlẹ Ẹka ṣiṣẹ

Mu asọtẹlẹ ẹka aimi ṣiṣẹ (Yipada sẹhin ati Ti ko gba siwaju) fun awọn itọnisọna ẹka.

mhartid CSR iye

· Hart ID Forukọsilẹ (mhartid) iye 0 ni aiyipada. · Fi iye kan laarin 0 ati 4094. · Ni ibamu pẹlu Altera FPGA Avalon Mutex Core HAL API.

Pa FSQRT & FDIV awọn ilana fun FPU

Yọ gbongbo-ojuami onigun lilefoofo (FSQRT) ati awọn iṣẹ pipin lilefoofo (FDIV) ni FPU.
· Waye imulation software lori awọn ilana mejeeji lakoko akoko ṣiṣe.

Alaye ti o jọmọ Ifibọ Agbeegbe IP Itọsọna olumulo – Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. yokokoro Taabu

Table 12. Debug Tab paramita

yokokoro Taabu

Apejuwe

Mu yokokoro ṣiṣẹ
Jeki Tunto lati Module yokokoro

2.1.1.3.3. Lockstep Tabili Tabili 13. Titiipa Taabu
Awọn paramita Jeki Titiipa Ipilẹṣẹ Aiyipada Akoko Ipari Igba Ilọsiwaju Atunto gbooro sii

Apejuwe · Mu eto titiipa mojuto meji ṣiṣẹ. Iye aiyipada ti akoko iseto lori ijade atunto (laarin 0 ati 255). · Jeki awọn iyan Extended Tun Interface fun o gbooro sii tun Iṣakoso. Nigbati o ba jẹ alaabo, fRSmartComp n ṣe Ipilẹ Iṣakoso Atunto.

2.1.1.3.4. Lo Taabu Ibere Tunto

Table 14. Lo Tun Ìbéèrè Tab paramita

Lo Taabu Ibere Tunto

Apejuwe

Fi Atunto Ibere ni wiwo

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· Ifihan agbara resetreq gbọdọ wa ni idaniloju titi ti ero isise yoo fi sọ ifihan agbara ack. Ikuna fun ifihan agbara lati wa ni idaniloju le fa ki ero isise wa ni ipo ti kii ṣe ipinnu.
· Imudaniloju ifihan agbara restreq ni ipo yokokoro ko ni ipa lori ipo ero isise naa.
· Oluṣeto Nios V ṣe idahun pe atunto naa ṣaṣeyọri nipasẹ sisọ ifihan agbara ack.
· Lẹhin ti awọn isise ti wa ni ifijišẹ tun, awọn itenumo ti awọn ack ifihan agbara le ṣẹlẹ ọpọ igba lorekore titi de-itẹnumọ ti awọn resetreq ifihan agbara.

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2.1.1.3.5. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 15.

Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ nigbati Muu Adarí Idilọwọ Ipele Ipele Core ti wa ni Pipa

Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ
Aṣoju atunto

Apejuwe
· Iranti alejo gbigba fekito atunto (adirẹsi atunto ero isise Nios V) nibiti koodu atunto gbe.
· O le yan eyikeyi iranti module ti a ti sopọ si awọn Nios V isise ilana titunto si ati ki o ni atilẹyin nipasẹ a Nios V isise bata sisan bi awọn ipilẹ oluranlowo.

Tun aiṣedeede

· Sọ aiṣedeede ti fekito atunto ojulumo si adirẹsi ipilẹ oluranlowo ti o yan. · Platform onise laifọwọyi pese a aiyipada iye fun awọn ipilẹ aiṣedeede.

Mu Alakoso Idilọwọ Idilọwọ Ipele Ipele Core (CLIC) ṣiṣẹ

· Mu CLIC ṣiṣẹ lati ṣe atilẹyin awọn idalọwọduro iṣaju-ofo ati ipo okunfa idalọwọduro atunto.
· Nigbati o ba ṣiṣẹ, o le tunto nọmba awọn idilọwọ Syeed, ṣeto awọn ipo okunfa, ki o si ṣe afihan diẹ ninu awọn idalọwọduro bi iṣaaju-emptive.

Idilọwọ Ipo Shadow Forukọsilẹ Files

Pato awọn iru idalọwọduro bi Taara, tabi Vectored Mu iforukọsilẹ ojiji ṣiṣẹ lati dinku yiyi ọrọ-ọrọ silẹ lori idalọwọduro.

Tabili 16.

Awọn ẹgẹ, Awọn imukuro ati Awọn Idilọwọ nigbati Mu Alakoso Idilọwọ Idilọwọ Ipele Core ti wa ni Titan

Ẹgẹ, Awọn imukuro, ati Idilọwọ

Awọn apejuwe

Aṣoju atunto
Tun aiṣedeede
Mu Alakoso Idilọwọ Idilọwọ Ipele Ipele Core (CLIC) ṣiṣẹ

· Iranti alejo gbigba fekito atunto (adirẹsi atunto ero isise Nios V) nibiti koodu atunto gbe.
· O le yan eyikeyi iranti module ti a ti sopọ si awọn Nios V isise ilana titunto si ati ki o ni atilẹyin nipasẹ a Nios V isise bata sisan bi awọn ipilẹ oluranlowo.
· Sọ aiṣedeede ti fekito atunto ojulumo si adirẹsi ipilẹ oluranlowo ti o yan. · Platform onise laifọwọyi pese a aiyipada iye fun awọn ipilẹ aiṣedeede.
· Mu CLIC ṣiṣẹ lati ṣe atilẹyin awọn idalọwọduro iṣaju-ofo ati ipo okunfa idalọwọduro atunto. Nigbati o ba ṣiṣẹ, o le tunto nọmba awọn idilọwọ Syeed, ṣeto awọn ipo okunfa,
ki o si designate diẹ ninu awọn idalọwọduro bi ami-emptive.

Ipo Idilọwọ

Pato awọn iru idalọwọduro bi Taara, Vectored, tabi CLIC.

Shadow Forukọsilẹ Files

· Mu iforukọsilẹ ojiji ṣiṣẹ lati dinku iyipada ọrọ-ọrọ lori idalọwọduro.
· Nfunni awọn ọna meji:
- Nọmba awọn ipele idalọwọduro CLIC
Nọmba ti awọn ipele idalọwọduro CLIC - 1: Aṣayan yii wulo nigbati o ba fẹ nọmba iforukọsilẹ file awọn ẹda lati baamu ni nọmba gangan ti awọn bulọọki M20K tabi M9K.
Mu ẹrọ isise Nios V ṣiṣẹ lati lo iforukọsilẹ ojiji files eyi ti o din o tọ yi pada lori lori da gbigbi.
Fun alaye siwaju sii nipa ojiji Forukọsilẹ files, tọka si Nios V Ilana Itọkasi Ilana.

Nọmba awọn orisun idalọwọduro Platform

· Sọ nọmba ti idalọwọduro iru ẹrọ laarin 16 si 2048.
Akiyesi: CLIC ṣe atilẹyin awọn igbewọle idalọwọduro 2064, ati awọn igbewọle idalọwọduro 16 akọkọ tun ni asopọ si oluṣakoso idalọwọduro ipilẹ.

CLIC Vector Table titete

· Ti pinnu ni aifọwọyi da lori nọmba awọn orisun idalọwọduro Syeed. · Ti o ba lo titete ti o wa ni isalẹ iye ti a ṣe iṣeduro, CLIC n mu ọgbọn pọ si
complexity nipa fifi ohun afikun paramọlẹ lati ṣe vectoring isiro. · Ti o ba lo titete ti o wa ni isalẹ iye ti a ṣe iṣeduro, eyi yoo mu abajade pọ si
kannaa complexity ni CLIC.
tesiwaju…

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Ẹgẹ, Awọn imukuro, ati Idilọwọ
Nọmba ti Awọn ipele Idilọwọ
Nọmba awọn ayo Idilọwọ fun ipele kan
Configurable da gbigbi polarity Atilẹyin eti jeki awọn idalọwọduro

Awọn apejuwe
· Sọ nọmba awọn ipele idalọwọduro pẹlu ipele afikun 0 fun koodu ohun elo. Awọn idilọwọ ti ipele ti o ga julọ le da gbigbi (ṣaaju-empt) oluṣakoso nṣiṣẹ fun idalọwọduro ipele-kekere.
· Pẹlu awọn ipele idalọwọduro ti kii-odo bi awọn aṣayan nikan fun awọn idilọwọ, koodu ohun elo nigbagbogbo wa ni ipele ti o kere julọ 0. Akiyesi: Iṣeto akoko-akoko ti ipele idalọwọduro ati pataki ni a ṣe ni iforukọsilẹ 8-bit kan. Ti nọmba awọn ipele idalọwọduro jẹ 256, ko ṣee ṣe lati tunto ayo idalọwọduro ni akoko ṣiṣe. Bibẹẹkọ, nọmba ti o pọju ti awọn ayo atunto jẹ 256 / (nọmba awọn ipele idalọwọduro – 1).
· Sọ nọmba ti awọn ayo idalọwọduro, eyiti CLIC nlo lati pinnu ilana ti a pe awọn alabojuto idalọwọduro iṣaaju. Akiyesi: Iṣọkan ti awọn iye alakomeji ti ipele idalọwọduro ti o yan ati ayo idalọwọduro ti o yan gbọdọ jẹ kere ju awọn die-die 8.
· Faye gba o lati tunto da gbigbi polarity nigba asiko isise. · Polarity aiyipada jẹ polarity rere.
O faye gba o laaye lati tunto ipo okunfa idalọwọduro lakoko asiko-ṣiṣe, ie ipele ti o ga tabi idasi-rere ti o fa (nigbati idalọwọduro polarity jẹ rere ni Configurable idalọwọduro polarity).
· Ipo okunfa aipe jẹ idalọwọduro ipele ti nfa.

Akiyesi:

Alaye ti o jọmọ Nios® V Ilana Itọkasi Olupilẹṣẹ

2.1.1.3.6. Memory atunto Tab

Table 17. Memory iṣeto ni Tab paramita

Ẹka

Taabu iṣeto ni Memory

Apejuwe

Awọn caches

Data kaṣe Iwon

· So awọn iwọn ti awọn data kaṣe. · Awọn iwọn to wulo jẹ lati 0 kilobytes (KB) si 16 KB. Pa kaṣe data nigbati iwọn ba jẹ 0 KB.

Ilana kaṣe Iwon

· Sọ iwọn kaṣe itọnisọna naa. · Awọn iwọn to wulo jẹ lati 0 KB si 16 KB. Pa kaṣe itọnisọna nigbati iwọn ba jẹ 0 KB.

Agbegbe Agbeegbe A ati B

Iwọn

· Sọ iwọn agbegbe agbeegbe.
· Awọn iwọn to wulo jẹ lati 64 KB si 2 gigabytes (GB), tabi Ko si. Yiyan Ko si ọkan ti o mu agbegbe agbeegbe duro.

Adirẹsi mimọ

· Sọtọ adirẹsi ipilẹ ti agbegbe agbeegbe lẹhin ti o yan iwọn naa.
Gbogbo awọn adirẹsi ni agbeegbe agbegbe gbe awọn uncacheable data wiwọle.
Adirẹsi ipilẹ agbegbe gbọdọ wa ni ibamu si iwọn agbegbe agbeegbe.

Ni wiwọ Tọkọtaya Iranti

Iwọn

· Sọ iwọn iranti ti a so pọ. - Awọn iwọn to wulo jẹ lati 0 MB si 512 MB.

Ipilẹ Adirẹsi Ibẹrẹ File

· Ṣe alaye adirẹsi ipilẹ ti iranti ti a so pọ. · Ni pato ibẹrẹ file fun ni wiwọ-pọ iranti.

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Akiyesi:

Ninu eto ero isise Nios V pẹlu ṣiṣiṣẹ kaṣe, o gbọdọ gbe awọn agbeegbe eto laarin agbegbe agbeegbe kan. O le lo awọn agbegbe agbeegbe lati ṣalaye iṣowo ti kii ṣe cacheable fun awọn agbeegbe bii UART, PIO, DMA, ati awọn miiran.

2.1.1.3.7. ECC Taabu

Table 18. ECC Tab
ECC Mu Wiwa aṣiṣe ṣiṣẹ ati Ijabọ Ipo
Mu Atunse Bit Nikan Kan ṣiṣẹ

Apejuwe
· Mu aṣayan yii ṣiṣẹ lati lo ẹya ECC fun awọn bulọọki Ramu inu ero isise Nios V. Awọn ẹya ECC ṣe awari to awọn aṣiṣe 2-bits ati fesi da lori ihuwasi atẹle:
- Ti o ba jẹ aṣiṣe bit ti o le ṣe atunṣe ati Mu Atunse Nikan Bit ṣiṣẹ, ero isise naa tẹsiwaju lati ṣiṣẹ lẹhin atunṣe aṣiṣe ninu opo gigun ti ẹrọ. Sibẹsibẹ, atunṣe ko han ninu awọn iranti orisun.
- Ti o ba jẹ aṣiṣe bit ti o le ṣe atunṣe ati Mu Atunse Nikan Bit ṣiṣẹ ti wa ni titan, ero isise naa tẹsiwaju lati ṣiṣẹ lẹhin atunse aṣiṣe ninu opo gigun ti ero isise ati awọn iranti orisun.
- Ti o ba jẹ aṣiṣe ti ko ṣe atunṣe, ero isise naa da iṣẹ rẹ duro.
Jeki atunse bit ẹyọkan lori awọn bulọọki iranti ti a fi sii ninu mojuto.

2.1.1.3.8. Aṣa itọnisọna Tab

Akiyesi:

Yi taabu wa nikan fun Nios V/g ero isise mojuto.

Aṣa ilana Nios V Aṣa ilana Hardware ni wiwo Table
Nios V Aṣa Ilana Software Makiro Table

Apejuwe
· Nios V isise nlo yi tabili lati setumo awọn oniwe-aṣa ilana alakoso atọkun.
· Awọn atọkun oluṣakoso itọnisọna aṣa ti a ti ṣalaye jẹ koodu ni iyasọtọ nipasẹ Opcode (CUSTOM0-3) ati awọn die-die 3 ti funct7[6:4].
· O le setumo soke si lapapọ 32 olukuluku aṣa itọnisọna atọkun.
· Nios V ero isise nlo yi tabili ti wa ni lo lati setumo aṣa ilana software encodings fun asọye aṣa itọnisọna atọkun.
Fun fifi koodu sọfitiwia aṣa aṣa kọọkan ti a ṣalaye, Opcode (CUSTOM0-3) ati awọn bits 3 ti funct7 [6:4] fifi ẹnọ kọ nkan gbọdọ ni ibamu si wiwo oluṣakoso itọnisọna aṣa ti asọye ni Tabili Interface Hardware Itọnisọna Aṣa.
O le lo funct7[6:4], funct7[3:0], ati funct3[2:0] lati setumo fifi koodu sii fun itọnisọna aṣa ti a fun, tabi ti a sọ bi Xs ti yoo kọja bi awọn ariyanjiyan itọnisọna afikun.
· Nios V isise pese telẹ aṣa ilana software encodings bi ti ipilẹṣẹ C-macros ni system.h, ki o si tẹle awọn R-Iru RISC-V ilana kika.
· Mnemonics le ṣee lo lati setumo awọn orukọ aṣa fun: — Awọn ti ipilẹṣẹ C-Macros ni system.h.
- Awọn mnemonics yokokoro GDB ti ipilẹṣẹ ni custom_instruction_debug.xml.

Alaye ti o jọmọ
AN 977: Nios V Processor Itọnisọna Aṣa Aṣa Fun alaye diẹ sii nipa awọn ilana aṣa ti o gba ọ laaye lati ṣe akanṣe ero isise Nios® V lati pade awọn iwulo ohun elo kan pato.

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2.1.2. Asọye System paati Design
Lo Apẹrẹ Platform lati ṣalaye awọn abuda ohun elo ti eto ero isise Nios V ati ṣafikun awọn paati ti o fẹ. Aworan ti o tẹle yii ṣe afihan apẹrẹ eto ero isise Nios V ipilẹ kan pẹlu awọn paati wọnyi: · Nios V processor core · On-Chip Memory · JTAG UART · Aago Aarin (aṣayan)(1)
Nigbati Iranti On-Chip tuntun ba ṣafikun si eto Onise Platform, ṣe Awọn alaye Eto amuṣiṣẹpọ lati ṣe afihan awọn paati iranti ti a ṣafikun ni ipilẹ. Ni omiiran, o le mu Amuṣiṣẹpọ Aifọwọyi ṣiṣẹ ni Apẹrẹ Platform lati ṣe afihan awọn ayipada paati tuntun laifọwọyi
Aworan 11. Eksample asopọ ti Nios V ero isise pẹlu miiran awọn pẹẹpẹẹpẹ ni Platform onise

(1) O ni aṣayan lati lo awọn ẹya Nios V Aago inu inu lati rọpo Aago Interval ita ni Onise Platform.

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O tun gbọdọ ṣalaye awọn pinni iṣẹ lati okeere bi conduit ninu eto Onise Platform rẹ. Fun example, atokọ pin iṣẹ eto FPGA to dara jẹ asọye bi isalẹ ṣugbọn ko ni opin si:
· Aago
· Tunto
· I/O awọn ifihan agbara
2.1.3. Pato Ipilẹ adirẹsi ati Idilọwọ awọn ayo ibeere
Lati pato bawo ni awọn paati ti a ṣafikun ninu apẹrẹ ṣe n ṣe ajọṣepọ lati ṣe eto kan, o nilo lati fi awọn adirẹsi ipilẹ fun paati aṣoju kọọkan ati fi awọn ipinnu idalọwọduro (IRQ) sọtọ fun J.TAG UART ati aago aarin. Olupese Platform pese aṣẹ kan - Fi Awọn adirẹsi Ipilẹ silẹ - eyiti o fi awọn adirẹsi ipilẹ to dara laifọwọyi si gbogbo awọn paati ninu eto kan. Sibẹsibẹ, o le ṣatunṣe awọn adirẹsi ipilẹ ti o da lori awọn iwulo rẹ.
Awọn atẹle jẹ diẹ ninu awọn itọnisọna fun yiyan awọn adirẹsi ipilẹ:
· Nios V ero isise mojuto ni o ni a 32-bit adirẹsi igba. Lati wọle si awọn paati aṣoju, adirẹsi ipilẹ wọn gbọdọ wa laarin 0x00000000 ati 0xFFFFFFFF.
· Awọn eto Nios V lo awọn ibakan aami lati tọka si awọn adirẹsi. O ko ni lati yan awọn iye adirẹsi ti o rọrun lati ranti.
· Awọn iye adirẹsi ti o ṣe iyatọ awọn paati pẹlu iyatọ adirẹsi ọkan-bit kan ṣe agbejade ohun elo ti o munadoko diẹ sii. O ko ni lati ṣapọ gbogbo awọn adirẹsi ipilẹ sinu iwọn adirẹsi ti o kere julọ nitori iṣiṣẹpọ le ṣẹda ohun elo ti ko ni agbara.
· Apẹrẹ Platform ko ṣe igbiyanju lati mö awọn paati iranti lọtọ pọ si ni iwọn iranti ti o tẹra. Fun example, ti o ba ti o ba fẹ ọpọ On-Chip Memory irinše addressable bi ọkan contiguous iranti ibiti, o gbọdọ kedere sọtọ mimọ adirẹsi.
Apẹrẹ Platform tun pese pipaṣẹ adaṣe kan - Fi awọn nọmba Idilọwọ ti o so awọn ami IRQ pọ lati gbe awọn abajade ohun elo to wulo. Sibẹsibẹ, yiyan awọn IRQ ni imunadoko nilo oye ti ihuwasi idahun eto gbogbogbo. Apẹrẹ Platform ko le ṣe awọn amoro ti ẹkọ nipa iṣẹ iyansilẹ IRQ ti o dara julọ.
Iwọn IRQ ti o kere julọ ni pataki julọ. Ninu eto pipe, Altera ṣeduro pe paati aago lati ni IRQ pataki ti o ga julọ, ie, iye ti o kere julọ, lati ṣetọju deede ti ami aago eto.
Ni awọn igba miiran, o le fi ayo ti o ga julọ si awọn agbeegbe akoko gidi (gẹgẹbi awọn olutona fidio), eyiti o nilo oṣuwọn idalọwọduro ti o ga ju awọn paati aago lọ.
Alaye ti o jọmọ
Itọsọna olumulo Quartus Prime Edition Pro: Alaye diẹ sii nipa ṣiṣẹda Eto kan pẹlu Onise Platform.

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2.2. Ṣiṣepọ Eto Onise Platform sinu Quartus Prime Project
Lẹhin ti ipilẹṣẹ apẹrẹ eto Nios V ni Platform Designer, ṣe awọn iṣẹ ṣiṣe atẹle lati ṣepọ module eto Nios V sinu iṣẹ apẹrẹ Quartus Prime FPGA. * Ṣe agbekalẹ module eto Nios V lẹsẹkẹsẹ ninu iṣẹ Quartus Prime · So awọn ifihan agbara lati module eto Nios V si awọn ifihan agbara miiran ninu ọgbọn FPGA · Fi ipo awọn pinni ti ara · Dina apẹrẹ FPGA
2.2.1. Instantiating awọn Nios V Prosessor Module ni Quartus Prime Project
Onise Platform ṣe ipilẹṣẹ nkan apẹrẹ module eto eyiti o le ṣe lẹsẹkẹsẹ ni Quartus Prime. Bii o ṣe ṣe imudara module eto da lori ọna titẹsi apẹrẹ fun iṣẹ akanṣe Quartus Prime lapapọ. Fun example, ti o ba ti o ba ni won lilo Verilog HDL fun oniru titẹsi, instantiate Verilog orisun eto module. Ti o ba fẹ lati lo ọna atọka Àkọsílẹ fun titẹsi apẹrẹ, tẹ aami module eto kan .bdf file.
2.2.2. Awọn ifihan agbara Nsopọ ati Yiyan Awọn ipo Pin Ti ara
Lati so apẹrẹ Altera FPGA rẹ pọ si apẹrẹ ipele igbimọ rẹ, ṣe awọn iṣẹ ṣiṣe wọnyi: · Ṣe idanimọ ipele-oke file fun apẹrẹ rẹ ati awọn ifihan agbara lati sopọ si Altera ita
FPGA ẹrọ pinni. Loye iru awọn pinni lati sopọ nipasẹ itọsọna olumulo apẹrẹ ipele igbimọ rẹ tabi
sikematiki. Pin awọn ifihan agbara ni apẹrẹ ipele oke si awọn ebute oko oju omi lori ẹrọ Altera FPGA rẹ pẹlu pin
awọn irinṣẹ iṣẹ iyansilẹ.
Eto Onise Platform rẹ le jẹ apẹrẹ ipele oke. Bibẹẹkọ, Altera FPGA tun le pẹlu ọgbọn afikun ti o da lori awọn iwulo rẹ ati nitorinaa ṣafihan ipele-oke aṣa aṣa file. Ipele oke file so Nios V isise eto module awọn ifihan agbara si awọn miiran Altera FPGA oniru kannaa.
Alaye ti o jọmọ Quartus Prime Pro Edition User Guide: Awọn ihamọ Apẹrẹ
2.2.3. Idinku Apẹrẹ Altera FPGA
Apẹrẹ eto Altera FPGA ti o tọ pẹlu awọn idiwọ apẹrẹ lati rii daju pe apẹrẹ pade pipade akoko ati awọn ibeere idiwọ ọgbọn miiran. O gbọdọ diwọ apẹrẹ Altera FPGA rẹ lati pade awọn ibeere wọnyi ni taara lilo awọn irinṣẹ ti a pese ni sọfitiwia Quartus Prime tabi awọn olupese EDA ẹni-kẹta. Sọfitiwia Quartus Prime nlo awọn idiwọ ti a pese lakoko ipele akopọ lati gba awọn abajade gbigbe to dara julọ.

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Alaye ti o jọmọ · Quartus Prime Pro Edition Itọsọna olumulo: Awọn ihamọ Oniru · Awọn alabaṣiṣẹpọ EDA Ẹni-kẹta · Quartus Prime Pro Edition Itọsọna olumulo: Oluyanju akoko
2.3. Ṣiṣeto Eto Iranti ero isise Nios V kan
Abala yii ṣapejuwe awọn iṣe ti o dara julọ fun yiyan awọn ẹrọ iranti ni eto ifibọ Apẹrẹ Platform pẹlu ero isise Nios V ati iyọrisi iṣẹ ṣiṣe to dara julọ. Awọn ẹrọ iranti ṣe ipa pataki ni imudarasi iṣẹ gbogbogbo ti eto ifibọ. Ifibọ eto iranti tọjú awọn ilana eto ati data.
2.3.1. Iranti iyipada
Iyatọ akọkọ ninu iru iranti jẹ iyipada. Iranti iyipada nikan di awọn akoonu inu rẹ mu nigba ti o pese agbara si ẹrọ iranti. Ni kete ti o ba yọ agbara kuro, iranti yoo padanu awọn akoonu rẹ.
Examples ti iyipada iranti ni Ramu, kaṣe, ati awọn iforukọsilẹ. Iwọnyi jẹ awọn oriṣi iranti iyara ti o mu iṣẹ ṣiṣe ṣiṣẹ. Altera ṣeduro pe ki o gbe ati ṣiṣẹ awọn ilana ero isise Nios V ni Ramu ki o so pọ Nios V IP core pẹlu On-Chip Memory IP tabi IP Interface Memory Ita fun iṣẹ ṣiṣe to dara julọ.
Lati mu ilọsiwaju ṣiṣẹ, o le ṣe imukuro afikun awọn paati aṣamubadọgba Onise Platform nipa ibaamu iru oluṣakoso data ero isise Nios V tabi iwọn pẹlu Ramu bata. Fun example, o le tunto On-Chip Memory II pẹlu kan 32-bits AXI-4 ni wiwo, eyi ti o ibaamu Nios V data ni wiwo faili.
Alaye ti o jọmọ · Awọn atọkun Iranti Itanna Ile-iṣẹ Atilẹyin IP · Iranti Chip (Ramu tabi ROM) Altera FPGA IP · On-Chip Memory II (Ramu tabi ROM) Altera FPGA IP · Nios V Ohun elo Processor Ṣiṣẹ-Ni-Ibi lati OCRAM loju iwe 54
2.3.1.1. On-Chip Memory iṣeto ni Ramu tabi ROM
O le tunto Altera FPGA On-Chip Memory IPs bi Ramu tabi ROM. · Ramu n pese agbara kika ati kikọ ati pe o ni ẹda iyipada. Ti o ba wa
booting awọn Nios V ero isise lati ẹya On-Chip Ramu, o gbọdọ rii daju bata akoonu ti wa ni dabo ati ki o ko ibaje ninu awọn iṣẹlẹ ti a tun nigba run akoko. Ti o ba jẹ pe ero isise Nios V ba n bẹrẹ lati ROM, eyikeyi kokoro software lori ero isise Nios V ko le ṣe atunṣe awọn akoonu ti On-Chip Memory ni aṣiṣe. Nitorinaa, idinku eewu ti ibajẹ sọfitiwia bata.
Alaye ti o jọmọ · Iranti Lori Chip (Ramu tabi ROM) Altera FPGA IP · On-Chip Memory II (Ramu tabi ROM) Altera FPGA IP · Nios V Ohun elo Processor Ṣiṣẹ-Ni-Ibi lati OCRAM loju iwe 54

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2.3.1.2. Awọn caches
Awọn iranti lori-chip ni a lo nigbagbogbo lati ṣe iṣẹ ṣiṣe kaṣe nitori airi kekere wọn. Awọn ero isise Nios V nlo iranti lori-chip fun itọnisọna rẹ ati awọn caches data. Agbara to lopin ti iranti lori-chip kii ṣe ọran fun awọn kaṣe nitori wọn jẹ deede kekere.
Awọn caches ni a lo nigbagbogbo labẹ awọn ipo wọnyi:
· Iranti deede wa ni pipa-ërún ati pe o ni akoko wiwọle to gun ju iranti on-chip lọ.
· Awọn apakan iṣẹ-pataki ti koodu sọfitiwia le baamu ni kaṣe itọnisọna, imudarasi iṣẹ ṣiṣe eto.
· Iṣe-pataki, apakan ti a lo nigbagbogbo ti data le baamu ni kaṣe data, imudarasi iṣẹ ṣiṣe eto.
Muu awọn caches ṣiṣẹ ni ero isise Nios V ṣẹda awọn ilana iranti, eyiti o dinku akoko iwọle iranti.
2.3.1.2.1. Agbegbe agbeegbe
Eyikeyi IP agbeegbe ti a fi sii, gẹgẹbi UART, I2C, ati SPI ko gbọdọ jẹ cache. Kaṣe jẹ iṣeduro gaan fun awọn iranti ita eyiti o kan nipasẹ akoko iwọle gigun, lakoko ti awọn iranti inu-chip le yọkuro nitori akoko iwọle kukuru wọn. Iwọ ko gbọdọ ṣaṣe eyikeyi awọn IP agbeegbe ti a fi sii, gẹgẹbi UART, I2C, ati SPI, ayafi fun awọn iranti. Eyi ṣe pataki nitori awọn iṣẹlẹ lati awọn ẹrọ ita, gẹgẹbi awọn ẹrọ aṣoju ti n ṣe imudojuiwọn awọn IPs rirọ, ko gba nipasẹ kaṣe ero isise, ni ọna ti ko gba nipasẹ ero isise naa. Bi abajade, awọn iṣẹlẹ wọnyi le ma ṣe akiyesi titi ti o fi fọ kaṣe naa, eyiti o le ja si ihuwasi airotẹlẹ ninu eto rẹ. Ni akojọpọ, agbegbe ti o ya aworan iranti ti awọn IP agbeegbe ifibọ ko ṣee ṣe ati pe o gbọdọ gbe laarin awọn agbegbe agbeegbe ero isise naa.
Lati ṣeto agbegbe agbeegbe, tẹle awọn igbesẹ wọnyi:
1. Ṣii awọn eto ká adirẹsi Map ni Platform onise.
2. Lilö kiri si maapu adirẹsi ti oluṣakoso itọnisọna ti ero isise ati Oluṣakoso data.
3. Ṣe idanimọ awọn agbeegbe ati awọn iranti ninu eto rẹ.
Aworan 12. Eksample of adirẹsi Map

Akiyesi: Awọn itọka buluu n tọka si awọn iranti. 4. Ṣe akojọpọ awọn agbeegbe:
a. Iranti bi cacheable b. Awọn agbeegbe bi uncacheable

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Table 19. Cacheable ati Uncacheable Region

Alabojuto

Maapu adirẹsi

Ipo

Agbegbe agbeegbe

Iwọn

Adirẹsi mimọ

olumulo_application_mem.s1

0x0 ~ 0x3ffff

Kaṣe

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 baiti N / A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 baiti (iwọn min jẹ 65536 awọn baiti)

0x54000

sysid_qsys_0.control_ẹrú

0x54080 ~ 0x54087

Ailokun

uart.avalon_jtag_ẹrú

0x54088 ~ 0x5408f

Ailokun

5. Ṣepọ awọn agbegbe agbeegbe pẹlu awọn iwọn pato wọn:
· Fun example, ti o ba ti awọn iwọn jẹ 65536 baiti, o ni ibamu si 0x10000 baiti. Nitorinaa, adirẹsi ipilẹ ti a gba laaye gbọdọ jẹ ọpọ ti 0x10000.
· CPU.dm_agent nlo adirẹsi ipilẹ ti 0x40000, eyiti o jẹ ọpọ ti 0x10000. Bi abajade, Agbegbe Agbeegbe A, pẹlu iwọn ti 65536 awọn baiti ati adirẹsi ipilẹ ti 0x40000, pade awọn ibeere.
· Adirẹsi ipilẹ ti gbigba awọn agbegbe ti ko ni ipamọ ni 0x54000 kii ṣe ọpọ ti 0x10000. O gbọdọ tun fi wọn si 0x60000 tabi ọpọ miiran ti 0x10000. Nitorinaa, Agbegbe Agbeegbe B, eyiti o ni iwọn ti 65536 awọn baiti ati adirẹsi ipilẹ ti 0x60000, ṣe itẹlọrun awọn ibeere.

Table 20. Cacheable ati Uncacheable Ekun pẹlu Reassignment

Alabojuto

Maapu adirẹsi

Ipo

Agbegbe agbeegbe

Iwọn

Adirẹsi mimọ

olumulo_application_mem.s1

0x0 ~ 0x3ffff

Kaṣe

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

Uncacheable 65536 baiti

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Kaṣe

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Kaṣe Ailokun Uncacheable Uncacheable Uncacheable

144 baiti (iwọn min jẹ 65536 awọn baiti)

0x60000

uart.avalon_jtag_ẹrú

0x60088 ~ 0x6008f

Ailokun

2.3.1.3. Ni wiwọ Tọkọtaya Iranti
Awọn iranti idapọmọra ni wiwọ (TCMs) ti wa ni imuse ni lilo iranti lori-chip bi lairi kekere wọn jẹ ki wọn baamu daradara si iṣẹ naa. Awọn TCM jẹ awọn iranti ti a ya aworan ni aaye adirẹsi aṣoju ṣugbọn ni wiwo iyasọtọ si microprocessor ati ni iṣẹ ṣiṣe giga, awọn ohun-ini aipe kekere ti iranti kaṣe. TCM tun pese wiwo abẹlẹ fun agbalejo ita. Awọn ero isise ati agbalejo ita ni ipele igbanilaaye kanna lati mu TCM naa.

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Akiyesi:

Nigba ti TCM subordinate ibudo ti wa ni ti sopọ si ohun ita ogun, o le wa ni han pẹlu kan yatọ si mimọ adirẹsi ju awọn mimọ adirẹsi sọtọ ni ero isise mojuto. Altera ṣe iṣeduro lati so awọn adirẹsi mejeeji pọ si iye kanna.

2.3.1.4. Ojú-iṣẹ́ Ìrántí Ita (EMIF)
EMIF (Interface Memory ita) ṣiṣẹ bakanna si SRAM (Imi-iranti Wiwọle ID Aimi), ṣugbọn o ni agbara ati pe o nilo itutu igbakọọkan lati ṣetọju akoonu rẹ. Awọn sẹẹli iranti ti o ni agbara ni EMIF kere pupọ ju awọn sẹẹli iranti aimi ni SRAM, eyiti o ni abajade agbara ti o ga julọ ati awọn ẹrọ iranti idiyele kekere.
Ni afikun si ibeere isọdọtun, EMIF ni awọn ibeere wiwo kan pato ti o ṣe pataki ohun elo oluṣakoso amọja. Ko dabi SRAM, eyiti o ni awọn laini adirẹsi ti o wa titi, EMIF ṣeto aaye iranti rẹ sinu awọn banki, awọn ori ila, ati awọn ọwọn. Yipada laarin awọn banki ati awọn ori ila ṣafihan diẹ ninu awọn oke, nitorinaa o gbọdọ farabalẹ paṣẹ awọn iraye si iranti lati lo EMIF daradara. EMIF tun multiplexes kana ati iwe adirẹsi lori awọn kanna adirẹsi ila, atehinwa awọn nọmba ti awọn pinni beere fun a fi EMIF iwọn.
Awọn ẹya iyara to ga julọ ti EMIF, gẹgẹbi DDR, DDR2, DDR3, DDR4, ati DDR5, fa awọn ibeere iduroṣinṣin ifihan agbara ti o muna ti awọn apẹẹrẹ PCB gbọdọ gbero.
Awọn ẹrọ EMIF ni ipo laarin awọn iye owo-doko julọ ati awọn iru Ramu ti o ga julọ ti o wa, ṣiṣe wọn ni aṣayan olokiki. Ẹya bọtini kan ti wiwo EMIF ni EMIF IP, eyiti o ṣakoso awọn iṣẹ ṣiṣe ti o nii ṣe pẹlu isodipupo pupọ, onitura, ati yi pada laarin awọn ori ila ati awọn banki. Apẹrẹ yii ngbanilaaye eto iyokù lati wọle si EMIF laisi iwulo lati loye faaji inu rẹ.

Jẹmọ Alaye Ita Memory atọkun IP Support Center

2.3.1.4.1. Adirẹsi Span Extender IP
Adirẹsi Span Extender Altera FPGA IP ngbanilaaye awọn atọkun ogun ti a ya aworan iranti lati wọle si maapu adirẹsi ti o tobi tabi kere ju iwọn awọn ifihan agbara adirẹsi wọn gba laaye. Adirẹsi Span Extender IP pin aaye ti a le koju si ọpọlọpọ awọn ferese lọtọ ki agbalejo le wọle si apakan ti o yẹ ti iranti nipasẹ window.
Adirẹsi Span Extender ko ṣe idinwo ogun ati awọn iwọn aṣoju si iṣeto 32-bit ati 64bit. O le lo Adirẹsi Span Extender pẹlu awọn window adirẹsi 1-64 bit.

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olusin 13. Adirẹsi Span Extender Altera FPGA IP
Adirẹsi Ọrọ Aṣoju

Adirẹsi Span Extender

Table ìyàwòrán
Ibudo Iṣakoso A

…

Iṣakoso Forukọsilẹ 0 Iṣakoso Forukọsilẹ Z-1

Adirẹsi Gbalejo ti gbooro H

Alaye ti o jọmọ
Itọsọna olumulo Quartus® Prime Pro Edition: Apẹrẹ Platform Tọkasi koko ọrọ Adirẹsi Span Extender Intel® FPGA IP fun alaye diẹ sii.

2.3.1.4.2. Lilo Adirẹsi Span Extender IP pẹlu Nios V Processor
Awọn 32-bit Nios V ero isise le koju soke 4 GB ti ohun adirẹsi akoko. Ti EMIF ba ni diẹ ẹ sii ju 4GB ti iranti lọ, o kọja akoko adiresi ti o ni atilẹyin ti o pọju, ti o nfi ẹrọ Oluṣeto Platform bi aṣiṣe. Adirẹsi Span Extender IP ni a nilo lati yanju ọran yii nipa pipin aaye adirẹsi EMIF kan si awọn ferese kekere pupọ.
Altera ṣeduro pe ki o gbero awọn aye atẹle wọnyi.

Table 21. Adirẹsi Span Extender paramita

Paramita

Niyanju Eto

Iwọn Data
Ti fẹ Titunto Baiti Adirẹsi Iwọn

Yan awọn 32-bits, eyiti o ṣe deede si ero isise 32-bit. Da lori iwọn iranti EMIF.

Àdírẹ́sì Ẹrú Ìbú Burstcount Ìbú

Yan 2 GB tabi kere si. Ipari adirẹsi ti o ku ti ero isise Nios V wa ni ipamọ fun awọn IPs rirọ miiran ti a fi sii.
Bẹrẹ pẹlu 1 ati maa pọ si iye yii lati mu ilọsiwaju sii.

Nọmba ti iha-windows

Yan 1 iha-window ti o ba n so EMIF pọ si ero isise Nios V gẹgẹbi itọnisọna ati iranti data, tabi mejeeji. Yipada laarin ọpọ awọn window-ipin lakoko ti ero isise Nios V n ṣiṣẹ lati EMIF jẹ eewu.

Mu Ibudo Iṣakoso Ẹrú ṣiṣẹ

Pa ibudo iṣakoso ẹrú kuro ti o ba n so EMIF pọ si ero isise Nios V gẹgẹbi itọnisọna ati/tabi iranti data. Awọn ifiyesi kanna bi Nọmba ti awọn window-ipin.

O pọju ni isunmọtosi ni Say

Bẹrẹ pẹlu 1 ati maa pọ si iye yii lati mu ilọsiwaju sii.

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Ṣe nọmba 14. Itọnisọna Nsopọ ati Oluṣakoso Data si Adirẹsi Span Extender

olusin 15. Adirẹsi Mapping

Ṣe akiyesi pe Adirẹsi Span Extender le wọle si gbogbo aaye iranti 8GB ti EMIF. Sibẹsibẹ, nipasẹ Adirẹsi Span Extender, ẹrọ isise Nios V le wọle si aaye iranti 1GB akọkọ ti EMIF nikan.

olusin 16. Simplified Block aworan atọka

Platform onise System

Ti o ku 3 GB

Nios V isise adirẹsi

igba ni fun ifibọ

NNioios sVV PProrocecsesosor r
M

asọ IPs ni kanna eto.
1 GB window

Adirẹsi Span

Extender

Nikan 1 GB akọkọ

ti iranti EMIF ti sopọ si Nios V

EMIF

isise.

8 GB
S

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2.3.1.4.3. Asọye Adirẹsi Span Extender Linker Memory Device 1. Setumo awọn adirẹsi Span Extender (EMIF) bi awọn atunto fekito. Ni omiiran, o le fi eto atunto ero isise Nios V si awọn iranti miiran, gẹgẹbi OCRAM tabi awọn ẹrọ filasi.
olusin 17. Awọn aṣayan pupọ bi Atunto Vector
Sibẹsibẹ, Apoti Atilẹyin Igbimọ (BSP) Olootu ko le forukọsilẹ laifọwọyi Adirẹsi Span Extender (EMIF) bi iranti to wulo. Ti o da lori yiyan ti o ṣe, o rii awọn ipo oriṣiriṣi meji bi o ṣe han ninu awọn isiro atẹle. Ṣe nọmba 18. Aṣiṣe BSP nigbati Itumọ Adirẹsi Span Extender (EMIF) gẹgẹbi Atunto Vector

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Ṣe nọmba 19. EMIF ti o padanu nigbati Itumọ Awọn iranti miiran bi Vector Tunto

2. O gbọdọ fi ọwọ kun Adirẹsi Span Extender (EMIF) ni lilo Fikun-un Ẹrọ Iranti, Fikun Agbegbe Iranti Asopọmọra, ati Fi Awọn aworan Abala Linker kun ni taabu BSP Linker Script.
3. Tẹle awọn igbesẹ wọnyi:
a. Ṣe ipinnu akoko adirẹsi ti Adirẹsi Span Extender ni lilo Maapu Iranti (Mofiample ni nọmba atẹle naa nlo Adirẹsi Span Extender ibiti o wa lati 0x0 si 0x3fff_ffff).
olusin 20. Memory Map

b. Tẹ Fi Memory Device, ati ki o fọwọsi ni da lori awọn alaye ninu rẹ oniru ká Memory Map: i. Orukọ ẹrọ: emif_ddr4. Akiyesi: Rii daju pe o daakọ orukọ kanna lati Maapu Iranti. ii. Adirẹsi mimọ: 0x0 iii. Iwọn: 0x40000000
c. Tẹ Fikun-un lati ṣafikun agbegbe iranti alasopọ tuntun kan:

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Table 22. Fifi Linker Memory Region

Awọn igbesẹ

Tunto Vector

emif_ddr4

Awọn iranti miiran

Fi titun Linker Memory Region ti a npe ni tun. Fi titun Linker Memory Region fun awọn

Orukọ agbegbe: tunto

emif_ddr4.

· Agbegbe Iwon: 0x20

· Orukọ agbegbe: emif_ddr4

· Ẹrọ iranti: emif_ddr4

· Agbegbe Iwon: 0x40000000

· Aiṣedeede iranti: 0x0

· Ẹrọ iranti: emif_ddr4

· Aiṣedeede iranti: 0x0

Fi titun Linker Memory Region fun awọn

emif_ddr4 ti o ku.

· Orukọ agbegbe: emif_ddr4

· Agbegbe Iwon: 0x3ffffffe0

· Ẹrọ iranti: emif_ddr4

· Aiṣedeede iranti: 0x20

Ṣe nọmba 21. Agbegbe Linker nigbati o n ṣalaye Adirẹsi Span Extender (EMIF) gẹgẹbi Atunto Vector

olusin 22. Linker Region nigbati asọye Miiran Memo bi Tun Vector
d. Ni kete ti emif_ddr4 ti wa ni afikun si BSP, o le yan fun eyikeyi Abala Linker.
olusin 23. Fikun Adirẹsi Span Extender (EMIF) Ni aṣeyọri

e. Foju ikilọ nipa ẹrọ Iranti emif_ddr4 ko han ni apẹrẹ SOPC.
f. Tẹsiwaju lati Ṣẹda BSP.
Alaye ti o jọmọ Iṣajuwe si Awọn ọna Booting Processor Nios V ni oju-iwe 51

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2.3.2. Non-iyipada Memory
Iranti ti kii ṣe iyipada ṣe idaduro awọn akoonu rẹ nigbati agbara ba wa ni pipa, ti o jẹ ki o jẹ yiyan ti o dara fun titoju alaye ti eto naa gbọdọ gba pada lẹhin iwọn agbara eto kan. Iranti ti kii ṣe iyipada ni igbagbogbo tọju koodu bata-isise, awọn eto ohun elo itẹramọṣẹ, ati data atunto Altera FPGA. Botilẹjẹpe iranti ti kii ṣe iyipada ni advantage of retaining its data when you remove the power, it is much slower compare to volatile memory, and often has more complex writing and erasing procedures. Non-volatile memory is also usually only guaranteed to be erasable a given number of times, after which it may fail.
ExampAwọn iranti ti kii ṣe iyipada pẹlu gbogbo awọn oriṣi filasi, EPROM, ati EEPROM. Altera ṣeduro ọ lati tọju awọn ṣiṣan ṣiṣan Altera FPGA ati awọn aworan eto Nios V sinu iranti ti kii ṣe iyipada, ati lo filasi ni tẹlentẹle bi ẹrọ bata fun awọn ilana Nios V.
Alaye ti o jọmọ
· Generic Serial Flash Interface Altera FPGA IP Itọsọna olumulo
Onibara Apoti ifiweranṣẹ Altera FPGA IP Itọsọna olumulo
2.4. Awọn aago ati Tunto Awọn iṣe ti o dara julọ
Loye bii aago ero isise Nios V ati ibugbe atunto ṣe n ṣe ajọṣepọ pẹlu gbogbo agbeegbe ti o sopọ mọ jẹ pataki. Eto ero isise Nios V ti o rọrun bẹrẹ pẹlu agbegbe aago kan, ati pe o le ni idiju pẹlu eto agbegbe aago pupọ nigbati agbegbe aago iyara ba kọlu pẹlu agbegbe aago o lọra. O nilo lati ṣe akiyesi ati loye bawo ni awọn oriṣiriṣi awọn ibugbe wọnyi ṣe n ṣe ilana ti atunto ati rii daju pe ko si awọn iṣoro arekereke eyikeyi.
Fun adaṣe ti o dara julọ, Altera ṣeduro gbigbe ero isise Nios V ati iranti bata ni agbegbe aago kanna. Ma ṣe tu ero isise Nios V silẹ lati tunto ni agbegbe aago iyara nigbati o ba bata lati iranti ti o ngbe ni agbegbe aago ti o lọra pupọ, eyiti o le fa aṣiṣe gbigba itọnisọna. O le nilo diẹ ninu awọn ilana afọwọṣe ju ohun ti Platform Designer pese nipasẹ aiyipada, ati gbero itusilẹ itusilẹ topology ni ibamu da lori ọran lilo rẹ. Ti o ba fẹ tun eto rẹ pada lẹhin ti o ba wa ni oke ati ṣiṣe fun igba diẹ, lo awọn ero kanna si ilana atunto eto ati ibeere ipilẹṣẹ atunto lẹhin.
2.4.1. Eto JTAG Aago
Pato awọn ihamọ aago ni gbogbo eto ero isise Nios V jẹ ero apẹrẹ eto pataki ati pe o nilo fun atunse ati ihuwasi ipinnu. Oluyanju akoko Quartus Prime n ṣe itupalẹ akoko aimi lati fọwọsi iṣẹ ṣiṣe akoko ti gbogbo ọgbọn inu apẹrẹ rẹ nipa lilo idiwọ-iwọn ile-iṣẹ, itupalẹ, ati ilana ijabọ.
Example 1. Ipilẹ 100 MHz Aago pẹlu 50/50 Ojuse Cycle ati 16 MHz JTAG Aago
************************************************************* # Ṣẹda 100MHz aago #************************************************ ṣẹda_clock -name {clk} -akoko 10 [gba_ports {clk}] #************************ Ṣẹda 16MHz JTAG Aago #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
Related Information Quartus Prime Timing Analyzer Cookbook
2.4.2. Tun Ibeere Interface
Nios V ero isise pẹlu ohun iyan tun ìbéèrè apo. Ohun elo ibeere atunto ni reset_req ati awọn ifihan agbara reset_req_ack.
Lati jeki ibeere atunto ni Platform Designer: 1. Lọlẹ Nios V Processor IP Parameter Editor. 2. Lori Eto Ibeere Atunto Lo, tan-an Fi Ibaraẹnisọrọ Tunto Ibẹrẹ
aṣayan.
olusin 24. Jeki Nios V Processor Ibere Ibere
Ifihan agbara reset_req n ṣiṣẹ bi idalọwọduro. Nigbati o ba so reset_req, o n beere lati tunto si mojuto. Awọn mojuto duro fun eyikeyi dayato akero idunadura lati pari awọn oniwe-isẹ. Fun example, ti o ba ti wa ni isunmọtosi ni wiwọle iranti idunadura, awọn mojuto duro fun pipe esi. Bakanna, mojuto gba eyikeyi idahun itọnisọna ni isunmọtosi ṣugbọn ko funni ni ibeere itọnisọna lẹhin gbigba ifihan agbara reset_req.
Iṣe atunṣe ni sisanwo atẹle yii: 1. Pari gbogbo awọn iṣẹ isunmọtosi 2. Fọ opo gigun ti inu 3. Ṣeto Eto Counter si fekito atunto 4. Tun ipilẹ to mojuto gbogbo iṣẹ atunto gba diẹ ninu awọn akoko aago. Reset_req naa gbọdọ wa ni idaniloju titi ti reset_req_ack yoo fi fi idi rẹ mulẹ ti n tọka si iṣẹ atunto mojuto ti pari ni aṣeyọri. Ikuna lati ṣe bẹ awọn abajade ni ipo mojuto ti kii ṣe ipinnu.

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2.4.2.1. Aṣoju lilo igba
· O le sọ ifihan agbara reset_req lati agbara-lori lati ṣe idiwọ mojuto ero isise Nios V lati bẹrẹ ipaniyan eto lati inu fekito atunto rẹ titi awọn ogun FPGA miiran ninu eto bẹrẹ iranti bata ero isise Nios V. Ni idi eyi, gbogbo subsystem le ni iriri kan mimọ hardware si ipilẹ. Awọn ero isise Nios V wa ni idaduro titilai ni ipo ibeere atunto titi ti awọn ọmọ-ogun FPGA miiran yoo bẹrẹ iranti bata ero isise naa.
· Ni a eto ibi ti o gbọdọ tun awọn Nios V ero isise mojuto lai disrupt awọn iyokù ti awọn eto, o le sọ awọn reset_req ifihan agbara lati mọ da duro awọn ti isiyi isẹ ti awọn mojuto ki o si tun awọn isise lati tun fekito ni kete ti awọn eto tu awọn reset_req_ack ifihan agbara.
· Alejo ita le lo wiwo ibeere atunto lati rọ awọn imuse ti awọn iṣẹ ṣiṣe wọnyi:
- Duro eto ero isise Nios V lọwọlọwọ.
- Fifuye eto tuntun sinu iranti bata ero isise Nios V.
- Gba ero isise naa laaye lati bẹrẹ ṣiṣe eto tuntun naa.
Altera ṣeduro rẹ lati ṣe ilana ilana akoko kan lati ṣe atẹle ipo ifihan agbara reset_req_ack. Ti mojuto ero isise Nios V ṣubu sinu ipo iduro ailopin ati duro fun idi aimọ, reset_req_ack ko le sọ titilai. Ilana akoko ipari gba ọ laaye lati:
· Ṣetumo akoko akoko imularada ati ṣe imularada eto pẹlu ipilẹ ipele eto.
Ṣe atunto ipele hardware kan.
2.4.3. Tun IP Tu silẹ
Awọn ẹrọ ti o da lori Altera SDM lo afiwera, faaji ti o da lori eka ti o pin kakiri iṣaro aṣọ mojuto kọja awọn apa lọpọlọpọ. Altera ṣeduro ọ lati lo Tu Tunto Altera FPGA IP bi ọkan ninu awọn igbewọle akọkọ si iyika atunto. Awọn ẹrọ orisun Intel® SDM pẹlu Stratix® 10, ati awọn ẹrọ AgilexTM. Awọn ẹrọ orisun idinamọ ko ni fowo nipasẹ ibeere yii.
Alaye ti o jọmọ
AN 891: Lilo Tu Tu Altera FPGA IP
2.5. Fifiranṣẹ Aṣoju Aiyipada
Onise Platform gba ọ laaye lati pato aṣoju aiyipada eyiti o ṣe bi aṣoju aiyipada idahun aṣiṣe. Aṣoju aiyipada ti o yan n pese iṣẹ esi aṣiṣe fun awọn ọmọ-ogun ti o gbiyanju awọn iraye si ti kii ṣe iyipada sinu maapu adirẹsi naa.
Awọn oju iṣẹlẹ wọnyi nfa iṣẹlẹ ti kii ṣe iyipada:
· Bosi idunadura aabo ipinle ṣẹ
· Wiwọle si iṣowo si agbegbe iranti aisọ asọye
· Iyatọ iṣẹlẹ ati be be lo.

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O yẹ ki o yan aṣoju aiyipada lati mu iru awọn iṣẹlẹ ṣiṣẹ, nibiti idunadura aisọye ti tun pada si aṣoju aiyipada ati lẹhinna dahun si ero isise Nios V pẹlu esi aṣiṣe.
Alaye ti o jọmọ
· Quartus Prime Pro Edition olumulo Itọsọna: Platform onise. Ṣiṣeto Aṣoju Aiyipada
· Quartus Prime Pro Edition olumulo Itọsọna: Platform onise. Idahun Aṣiṣe Ẹrú Altera FPGA IP
Github – Awọn Irinṣẹ Atunto Ipilẹṣẹ fun Qsys

2.6. Ṣiṣe Aṣoju UART fun Titẹ
Titẹ sita wulo fun ṣiṣatunṣe ohun elo sọfitiwia, bakannaa fun abojuto ipo eto rẹ. Altera ṣe iṣeduro titẹ alaye ipilẹ gẹgẹbi ifiranṣẹ ibẹrẹ, ifiranṣẹ aṣiṣe, ati ilọsiwaju ipaniyan ti ohun elo sọfitiwia.
Yẹra fun lilo iṣẹ ikawe printf () labẹ awọn ipo wọnyi: · Ile-ikawe printf () jẹ ki ohun elo naa duro ti ko ba si agbalejo ti n kajade.
Eyi wulo fun JTAG UART nikan. · Ile-ikawe printf () n gba iye iranti eto pupọ.

2.6.1. Idilọwọ awọn ibùso nipasẹ JTAG UART

Table 23. Awọn iyatọ laarin UART Ibile ati JTAG UART

UART Iru Ibile UART

Apejuwe
Gbigbe data ni tẹlentẹle laibikita boya agbalejo ita n tẹtisi. Ti ko ba si ogun ti o ka data ni tẹlentẹle, data naa ti sọnu.

JTAG UART

Kọ data ti a tan kaakiri si ifipamọ iṣelọpọ ati gbarale agbalejo ita lati ka lati inu ifipamọ lati sọ di ofo.

Awọn JTAG Iwakọ UART n duro de igba ti ifipajade ti kun. Awọn JTAG Awakọ UART n duro de agbalejo ita lati ka lati inu ifipamọ iṣelọpọ ṣaaju kikọ data atagba diẹ sii. Ilana yi idilọwọ awọn isonu ti atagba data.
Bibẹẹkọ, nigbati a ko nilo atunṣe eto, gẹgẹbi lakoko iṣelọpọ, awọn eto ifibọ ti wa ni ran lọ laisi PC ogun ti o sopọ si JTAG UART. Ti eto ba yan JTAG UART gẹgẹbi aṣoju UART, o le fa eto idaduro nitori ko si ogun ita ti o sopọ.
Lati ṣe idiwọ idaduro nipasẹ JTAG UART, lo awọn aṣayan wọnyi:

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Table 24. Idena lori Stalling nipasẹ JTAG UART

Awọn aṣayan
Ko si UART ni wiwo ati ki o iwakọ bayi
Lo wiwo UART miiran ati awakọ
Ṣetọju JTAG UART ni wiwo (laisi awakọ)

Lakoko Idagbasoke Hardware (ni Apẹrẹ Platform)

Lakoko Idagbasoke sọfitiwia (ni Olootu Package Support Board)

Yọ JTAG UART lati eto

Tunto hal.stdin, hal.stdout ati hal.stderr bi Ko si.

Rọpo JTAG UART pẹlu asọ miiran Tunto hal.stdin, hal.stdout ati hal.stderr

UART IP

pẹlu awọn miiran asọ UART IP.

Ṣetọju JTAG UART ninu eto

Tunto hal.stdin, hal.stdout ati hal.stderr bi Ko si ọkan ninu Olootu Package Support Board.
Pa JTAG UART iwakọ ni BSP Driver taabu.

2.7. JTAG Awọn ifihan agbara
module yokokoro ero isise Nios V nlo JTAG ni wiwo fun software ELF download ati software n ṣatunṣe aṣiṣe. Nigbati o ba ṣatunṣe apẹrẹ rẹ pẹlu JTAG wiwo, JTAG awọn ifihan agbara TCK, TMS, TDI, ati TDO ti wa ni imuse gẹgẹbi apakan ti apẹrẹ. Ni pato, JTAG awọn ihamọ ifihan agbara ni gbogbo eto ero isise Nios V jẹ ero apẹrẹ eto pataki ati pe o nilo fun atunse ati ihuwasi ipinnu.
Altera ṣeduro pe eyikeyi igbohunsafẹfẹ aago eto apẹrẹ jẹ o kere ju igba mẹrin JTAG igbohunsafẹfẹ aago lati rii daju wipe on-chip instrumentation (OCI) mojuto awọn iṣẹ daradara.
Alaye ti o jọmọ · Quartus® Iwe Onjewiwa Oluyanju akoko akoko akọkọ: JTAG Awọn ifihan agbara
Fun alaye siwaju sii nipa JTAG awọn itọnisọna awọn ihamọ akoko. KDB: Kini idi ti igbasilẹ niosv ṣe kuna pẹlu ero isise Nios® V/m ti kii-pipelined ni
JTAG igbohunsafẹfẹ 24MHz tabi 16Mhz?
2.8. Ti o dara ju Platform onise System Performance
Apẹrẹ Platform n pese awọn irinṣẹ fun imudara iṣẹ ṣiṣe ti ọna asopọ eto fun awọn apẹrẹ Altera FPGA.

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olusin 25. Iṣapeye Examples

Awọn example han ninu nọmba rẹ ṣe afihan awọn igbesẹ wọnyi:
1. Ṣe afikun Pipeline Bridge lati dinku awọn ọna pataki nipa gbigbe si: a. Laarin Alakoso Itọsọna ati awọn aṣoju rẹ b. Laarin Oluṣakoso Data ati awọn aṣoju rẹ
2. Waye Otitọ Meji ibudo On-Chip Ramu, pẹlu kọọkan ibudo igbẹhin si awọn ilana ati awọn Data Manager lẹsẹsẹ.

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Tọkasi awọn ọna asopọ ti o ni ibatan ti o wa ni isalẹ, eyiti o ṣafihan awọn ilana fun gbigbe awọn irinṣẹ to wa ati awọn iṣowo ti imuse kọọkan.
Alaye ti o jọmọ · Quartus® Prime Pro Edition Itọsọna olumulo: Apẹrẹ Platform
Tọkasi koko-ọrọ Nmudara Iṣe Ṣiṣe Onise Platform fun alaye diẹ sii. · Quartus® Prime Standard Edition Itọsọna Olumulo: Apẹrẹ Platform Tọkasi koko-ọrọ naa Iṣe-ṣiṣe Oluṣeto Platform Didara fun alaye diẹ sii.

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3. Nios V Prosessor Software System Design
Ipin yii ṣapejuwe ṣiṣan idagbasoke sọfitiwia ero isise Nios V ati awọn irinṣẹ sọfitiwia ti o le lo ninu idagbasoke eto apẹrẹ ifibọ rẹ. Awọn akoonu Sin bi ohun loriview ṣaaju idagbasoke eto sọfitiwia ero isise Nios V.
olusin 26. Software Design Flow
Bẹrẹ

Ṣe ina BSP ni Apẹrẹ Platform Lilo Olootu BSP

Ṣe ina BSP Lilo Ikarahun Aṣẹ Nios V
Ṣẹda Ohun elo CMake Kọ File Lilo Nios V Command Shell

Akiyesi:

Ṣe agbewọle BSP ati Ohun elo CMake Kọ File
Kọ Nios V Processor Ohun elo lilo awọn
RiscFree IDE fun Intel FPGA

Kọ ohun elo Nios V Processor nipa lilo eyikeyi
Olootu koodu orisun laini aṣẹ, CMake, ati Ṣe
ase
Ipari

Altera ṣeduro pe ki o lo ohun elo idagbasoke Altera FPGA kan tabi igbimọ afọwọkọ aṣa fun idagbasoke sọfitiwia ati ṣatunṣe aṣiṣe. Ọpọlọpọ awọn agbeegbe ati awọn ẹya ipele eto wa nikan nigbati sọfitiwia rẹ nṣiṣẹ lori igbimọ gangan.

© Altera Corporation. Altera, aami Altera, aami 'a', ati awọn ami Altera miiran jẹ aami-iṣowo ti Altera Corporation. Altera ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Altera ko gba ojuse tabi layabiliti ti o waye lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Altera. A gba awọn alabara Altera nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

3. Nios V Prosessor Software System Design 726952 | 2025.07.16
3.1. Nios V Prosessor Software Sisan
3.1.1. Board Support Package Project
Ise agbese Nios V Board Support Package (BSP) jẹ ile-ikawe amọja ti o ni koodu atilẹyin eto-pato. BSP kan n pese agbegbe asiko asiko sọfitiwia ti a ṣe adani fun ero isise kan ninu eto ohun elo ero isise Nios V kan.
Sọfitiwia Quartus Prime n pese Olootu Package Support Nios V Board ati awọn irinṣẹ ohun elo niosv-bsp lati yipada awọn eto ti o ṣakoso ihuwasi ti BSP.
BSP ni awọn eroja wọnyi ninu: · Layer abstraction Hardware · Awakọ ẹrọ · Awọn idii sọfitiwia aṣayan · Eto iṣẹ ṣiṣe akoko gidi iyan
3.1.2. Ohun elo Project
Ise agbese ohun elo Nios VC/C++ ni awọn ẹya wọnyi: · Ni akojọpọ koodu orisun ati CMekeLists.txt.
— CMakeLists.txt ṣe akopọ koodu orisun ati so pọ pẹlu BSP kan ati ọkan tabi diẹ sii awọn ile-ikawe yiyan, lati ṣẹda ọkan .elf file
· Ọkan ninu awọn orisun files ni akọkọ iṣẹ (). Pẹlu koodu ti o pe awọn iṣẹ ni awọn ile-ikawe ati awọn BSPs.
Altera n pese ohun elo ohun elo niosv-app ni awọn irinṣẹ ohun elo sọfitiwia Quartus Prime lati ṣẹda Ohun elo CMakeLists.txt, ati RiscFree IDE fun Altera FPGA lati yi koodu orisun pada ni agbegbe orisun-Eclipse.
3.2. Awọn Irinṣẹ Idagbasoke Altera FPGA
Awọn ero isise Nios V ṣe atilẹyin awọn irinṣẹ wọnyi fun idagbasoke sọfitiwia: · Atọka Olumulo Aworan (GUI) – Awọn irinṣẹ idagbasoke ayaworan ti o wa ninu
mejeeji Windows* ati Lainos* Awọn ọna ṣiṣe (OS). - Nios V Board Support Package Olootu (Nios V BSP Olootu) - Ashling RiscFree IDE fun Altera FPGAs · Command-Line Tools (CLI) - Awọn irinṣẹ idagbasoke ti o bẹrẹ lati Nios V Command Shell. Ọpa kọọkan n pese iwe ti ara rẹ ni irisi iranlọwọ ti o wa lati laini aṣẹ. Ṣii ikarahun aṣẹ Nios V ki o tẹ aṣẹ wọnyi: - iranlọwọ view akojọ Iranlọwọ. - Nios V Awọn irinṣẹ Awọn ohun elo — File Awọn irinṣẹ Iyipada ọna kika - Awọn Irinṣẹ Ohun elo miiran

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Table 25. GUI Irinṣẹ ati Òfin-ila Tools Lakotan

Iṣẹ-ṣiṣe

GUI Ọpa

Ọpa ila-aṣẹ

Ṣiṣẹda BSP kan

Nios V BSP Olootu

Ninu sọfitiwia Quartus Prime Pro Edition: niosv-bsp -c -s=<.qsys file> -t= Awọn eto [Awọn aṣayan].bsp
Ni Quartus Prime Standard Edition sọfitiwia: niosv-bsp -c -s=<.sopcinfo file> -t= Awọn eto [Awọn aṣayan].bsp

Ṣiṣẹda BSP kan nipa lilo .bsp ti o wa file
Nmu imudojuiwọn BSP kan

Nios V BSP Olootu Nios V BSP Olootu

niosv-bsp -g [Aṣayan] settings.bsp niosv-bsp -u [OPTIONS] settings.bsp

Ṣiṣayẹwo BSP kan

Nios V BSP Olootu

niosv-bsp -q -E = Awọn eto [Awọn aṣayan].bsp

Ṣiṣẹda ohun elo

–

niosv-app -a= -b= -s= files liana> [OPTIONS]

Ṣiṣẹda a olumulo ìkàwé

–

niosv-app -l= -s= files liana> -p= [Awọn aṣayan]

Ṣatunṣe ohun elo Ṣiṣe atunṣe ile-ikawe olumulo kan Ṣiṣe ohun elo kan

RiscFree IDE fun Altera FPGAs
RiscFree IDE fun Altera FPGAs
RiscFree IDE fun Altera FPGAs

Eyikeyi olootu orisun laini aṣẹ
Eyikeyi olootu orisun laini aṣẹ
· ṣe · cmake

Ilé a olumulo ìkàwé

RiscFree IDE fun Altera FPGAs

· ṣe · cmake

Gbigba ohun elo ELF kan
Yiyipada awọn .elf file

RiscFree IDE fun Altera FPGAs
–

niosv-gbigba
· elf2flash · elf2hex

Alaye ti o jọmọ
Ayika Idagbasoke Integrated Ashling RiscFree (IDE) fun Itọsọna olumulo Altera FPGAs

3.2.1. Nios V Processor Board Support Package Olootu
O le lo Olootu BSP ero isise Nios V lati ṣe awọn iṣẹ ṣiṣe wọnyi: · Ṣẹda tabi ṣe atunṣe ero isise Nios V iṣẹ akanṣe BSP · Ṣatunkọ eto, awọn agbegbe asopọ, ati awọn aworan aworan apakan · Yan awọn akojọpọ sọfitiwia ati awakọ ẹrọ.
Awọn agbara ti Olootu BSP pẹlu awọn agbara ti awọn ohun elo niosv-bsp. Eyikeyi iṣẹ akanṣe ti a ṣẹda ninu Olootu BSP tun le ṣẹda nipa lilo awọn ohun elo laini aṣẹ.

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Akiyesi:

Fun sọfitiwia Ẹya Standard Quartus Prime, tọka si AN 980: Nios V Processor Quartus Prime Software Atilẹyin fun awọn igbesẹ lati pe GUI Olootu BSP.

Lati ṣe ifilọlẹ Olootu BSP, tẹle awọn igbesẹ wọnyi: 1. Ṣii Platform Designer, ati lilö kiri si File akojọ aṣayan.
a. Lati ṣii eto BSP to wa tẹlẹ file, tẹ Ṣii… b. Lati ṣẹda BSP tuntun, tẹ BSP Tuntun… 2. Yan taabu Olootu BSP ki o pese awọn alaye ti o yẹ.

olusin 27. Ifilọlẹ BSP Olootu

Alaye ti o jọmọ AN 980: Nios V Processor Quartus Prime Software Support
3.2.2. RiscFree IDE fun Altera FPGAs
IDE RiscFree fun Altera FPGAs jẹ IDE ti o da lori oṣupa fun ero isise Nios V. Altera ṣeduro pe ki o ṣe agbekalẹ sọfitiwia ero isise Nios V ni IDE yii fun awọn idi wọnyi: · Awọn ẹya ti ni idagbasoke ati rii daju pe o ni ibamu pẹlu Nios V.
isise Kọ sisan. · Ni ipese pẹlu gbogbo awọn irinṣẹ irinṣẹ pataki ati awọn irinṣẹ atilẹyin eyiti o fun ọ laaye
lati awọn iṣọrọ bẹrẹ Nios V isise idagbasoke.
Alaye ti o jọmọ Ashling RiscFree Integrated Development Environment (IDE) fun Itọsọna olumulo Altera FPGAs
3.2.3. Nios V Awọn irinṣẹ Awọn ohun elo
O le ṣẹda, yipada, ati kọ awọn eto Nios V pẹlu awọn aṣẹ ti a tẹ ni laini aṣẹ tabi ti a fi sinu iwe afọwọkọ kan. Awọn irinṣẹ laini aṣẹ Nios V ti a ṣalaye ni apakan yii wa ninu /niosv/bin liana.

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Table 26. Nios V Awọn irinṣẹ Awọn ohun elo

Awọn irinṣẹ Laini-aṣẹ

Lakotan

niosv-app niosv-bsp niosv-ṣe igbasilẹ niosv-shell niosv-stack-iroyin

Lati ṣe ipilẹṣẹ ati tunto iṣẹ akanṣe kan.
Lati ṣẹda tabi ṣe imudojuiwọn awọn eto BSP kan file ati ṣẹda BSP files. Lati ṣe igbasilẹ ELF file si ẹrọ isise Nios® V.
Lati ṣii Nios V Command Shell. Lati sọ fun ọ aaye iranti osi-oke ti o wa si ohun elo rẹ .elf fun akopọ tabi lilo òkiti.

3.2.4. File Awọn irinṣẹ Iyipada ọna kika

File iyipada ọna kika jẹ pataki nigbakan nigba gbigbe data lati ohun elo kan si omiiran. Awọn file awọn irinṣẹ iyipada ọna kika wa ninu
liana fifi sori software>/niosv/bin liana.

Tabili 27. File Awọn irinṣẹ Iyipada ọna kika

Awọn irinṣẹ Laini Aṣẹ elf2flash elf2hex

Lakotan Lati tumọ .elf file to .srec kika fun filasi iranti siseto. Lati tumọ .elf file to .hex kika fun ibẹrẹ iranti.

3.2.5. Awọn Irinṣẹ Ohun elo miiran

O le nilo awọn irinṣẹ laini aṣẹ atẹle nigbati o ba kọ eto orisun ero isise Nios V kan. Awọn irinṣẹ laini aṣẹ wọnyi boya pese nipasẹ Intel ni /quartus/bin tabi ti o gba lati
ìmọ-orisun irinṣẹ.

Table 28. Miiran Òfin-Line Tools

Awọn irinṣẹ Laini-aṣẹ

Iru

Lakotan

juart-ebute

Intel-pese

Lati ṣe atẹle stdout ati stderr, ati lati pese igbewọle si ero isise Nios® V
subsystem nipasẹ stdin. Ọpa yii kan si JTAG UART IP nigbati o ba ti sopọ si ero isise Nios® V.

ìmọocd

Ti pese Intel Lati ṣiṣẹ OpenOCD.

openocd-cfg-gen

Ti pese Intel · Lati ṣe agbekalẹ iṣeto OpenOCD file. · Lati ṣafihan JTAG pq ẹrọ atọka.

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726952 | 2025.07.16 Firanṣẹ esi
4. Nios V isise iṣeto ni ati Booting Solutions
O le tunto ero isise Nios V lati bata ati ṣiṣẹ sọfitiwia lati awọn ipo iranti oriṣiriṣi. Iranti bata jẹ Filaṣi Quad Serial Peripheral Interface (QSPI), Iranti Lori Chip (OCRAM), tabi Iranti Isopọ Ni wiwọ (TCM).
Alaye ti o jọmọ · Awọn ipo Nfa agbara-soke loju iwe 193 · Awọn okunfa agbara-soke
Fun alaye siwaju sii nipa awọn okunfa agbara-soke.
4.1. Ifihan
Awọn ero isise Nios V ṣe atilẹyin awọn oriṣi meji ti awọn ilana bata: · Execute-in-Place (XIP) nipa lilo iṣẹ alt_load () · Eto ti a daakọ si Ramu nipa lilo oludaakọ bata. Idagbasoke awọn eto ifibọ Nios V da lori Layer abstraction hardware (HAL). HAL naa n pese eto agberu bata kekere kan (ti a tun mọ si adaakọ bata) ti o daakọ awọn apakan asopọ ti o yẹ lati iranti bata si ipo akoko ṣiṣe wọn ni akoko bata. O le pato eto naa ati awọn ipo akoko ṣiṣe iranti data nipa ṣiṣakoso awọn eto Olootu Package Support Board (BSP). Yi apakan apejuwe: · Nios V isise bata copier ti orunkun rẹ Nios V isise eto gẹgẹ bi
awọn aṣayan iranti bata · Nios V isise booting awọn aṣayan ati gbogbo sisan · Nios V siseto solusan fun awọn ti a ti yan bata iranti
4.2. Awọn ohun elo asopọ
Nigbati o ba ṣe ipilẹṣẹ iṣẹ ero isise Nios V, Olootu BSP n ṣe agbejade ọna asopọ meji ti o ni ibatan files: · linker.x: The linker pipaṣẹ file pe ohun elo ti ipilẹṣẹ ṣefile nlo
lati ṣẹda alakomeji .elf file. · linker.h: Ni alaye nipa awọn ifilelẹ iranti linker. Gbogbo awọn atunṣe eto ọna asopọ ti o ṣe si iṣẹ akanṣe BSP ni ipa lori awọn akoonu ti awọn ọna asopọ meji wọnyi files. Gbogbo ohun elo ero isise Nios V ni awọn apakan ọna asopọ atẹle wọnyi:
© Altera Corporation. Altera, aami Altera, aami 'a', ati awọn ami Altera miiran jẹ aami-iṣowo ti Altera Corporation. Altera ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Altera ko gba ojuse tabi layabiliti ti o waye lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Altera. A gba awọn alabara Altera nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

4. Nios V isise iṣeto ni ati Booting Solutions 726952 | 2025.07.16

Table 29. Linker Section

.ọrọ

Awọn apakan Linker

.rodata

.rwdata

.bss

.òkiti

.akopọ

Awọn apejuwe Executable koodu. Eyikeyi data kika-nikan ti a lo ninu ipaniyan ti eto naa. Awọn ile itaja kika-kikọ data ti a lo ninu ipaniyan ti eto naa. Ni data aimi ti ko ni ibẹrẹ ninu. Ni iranti soto ni agbara. Tọju awọn paramita iṣẹ-ipe ati data igba diẹ miiran.

O le ṣafikun awọn apakan ọna asopọ afikun si .elf file lati mu koodu aṣa ati data. Awọn apakan ọna asopọ wọnyi ni a gbe si awọn agbegbe iranti ti a npè ni, asọye lati badọgba pẹlu awọn ẹrọ iranti ti ara ati awọn adirẹsi. Nipa aiyipada, Olootu BSP n ṣe ipilẹṣẹ awọn abala asopọ wọnyi laifọwọyi. Sibẹsibẹ, o le ṣakoso awọn apakan ọna asopọ fun ohun elo kan pato.

4.2.1. Iwa asopọ
Abala yii ṣapejuwe ihuwasi sisopọ aiyipada Olootu BSP ati bii o ṣe le ṣakoso ihuwasi sisopọ.

4.2.1.1. Asopọmọra BSP aiyipada
Lakoko iṣeto BSP, awọn irinṣẹ ṣe awọn igbesẹ wọnyi laifọwọyi:
1. Fi awọn orukọ agbegbe iranti: Fi orukọ kan si ẹrọ iranti eto kọọkan ki o ṣafikun orukọ kọọkan si ọna asopọ file bi agbegbe iranti.
2. Wa iranti ti o tobi julọ: Ṣe idanimọ agbegbe iranti kika-ati-kọ ti o tobi julọ ni ọna asopọ file.
3. Fi awọn apakan asopọ: Fi awọn apakan asopọ asopọ aiyipada (.ọrọ, .rodata, .rwdata, .bss, .heap, and .stack) si agbegbe iranti ti a mọ ni igbesẹ ti tẹlẹ.
4. Kọ files: Kọ linker.x ati linker.h files.
Ni deede, ero ipin apakan ọna asopọ ṣiṣẹ lakoko ilana idagbasoke sọfitiwia nitori pe ohun elo naa jẹ iṣeduro lati ṣiṣẹ ti iranti ba tobi to.
Awọn ofin fun ihuwasi ọna asopọ aiyipada wa ninu awọn iwe afọwọkọ Tcl ti Altera ti ipilẹṣẹ bsp-set-defaults.tcl ati bsp-linker-utils.tcl ti a rii ninu /niosv/awọn iwe afọwọkọ/bsp-itọsọna aiyipada. Aṣẹ niosv-bsp n pe awọn iwe afọwọkọ wọnyi. Maṣe ṣe atunṣe awọn iwe afọwọkọ wọnyi taara.

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4.2.1.2. Asopọmọra BSP atunto
O le ṣakoso ihuwasi sisopọ aiyipada ni taabu Afọwọkọ Linker ti Olootu BSP. Ṣe afọwọyi iwe afọwọkọ ọna asopọ ni lilo awọn ọna wọnyi: · Fi agbegbe iranti kun: Ṣe maapu orukọ agbegbe iranti si ẹrọ iranti ti ara. Ṣafikun aworan agbaye: Ṣe maapu orukọ apakan si agbegbe iranti kan. BSP
Olootu faye gba o lati view maapu iranti ṣaaju ati lẹhin ṣiṣe awọn ayipada.

4.3. Nios V Prosessor Booting Awọn ọna

Awọn ọna diẹ lo wa lati ṣe bata ero isise Nios V ni awọn ẹrọ Altera FPGA. Awọn ọna lati ṣe bata ero isise Nios V yatọ ni ibamu si yiyan iranti filasi ati awọn idile ẹrọ.

Table 30. Atilẹyin Flash Memories pẹlu Ọwọ Boot Aw

Awọn iranti Boot atilẹyin

Ẹrọ

Filaṣi On-Chip (fun iṣeto inu)

Awọn ẹrọ 10 ti o pọju nikan (pẹlu On-Chip Flash IP)

Idi Gbogbogbo QSPI Flash (fun data olumulo nikan)

Gbogbo awọn ẹrọ FPGA ti o ni atilẹyin (pẹlu Generic Serial Flash Interface FPGA IP)

Iṣeto QSPI Filaṣi (fun iṣeto ni Serial ti nṣiṣe lọwọ)

Iṣakoso Àkọsílẹ-orisun
awọn ẹrọ (pẹlu Generic
Serial Flash Interface Intel FPGA IP)(2)

Nios V Prosessor Booting Awọn ọna

Ohun elo asiko isise Location

Copier bata

Ohun elo ero isise Nios V ṣiṣẹ ni aaye lati Filaṣi On-Chip

Filaṣi On-Chip (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load () iṣẹ

Ohun elo ero isise Nios V daakọ lati On-Chip Filaṣi si Ramu ni lilo adakọ bata

OCRAM / Ita Ramu

Tun lo Bootloader nipasẹ GSFI

Ohun elo ero isise Nios V ti n ṣiṣẹ ni aaye lati idi gbogbogbo QSPI filasi

Idi gbogbogbo QSPI filasi (XIP) + OCRAM/ Ramu ita (fun awọn apakan data kikọ)

alt_load () iṣẹ

Ohun elo ero isise Nios V daakọ lati idi gbogbogbo QSPI filasi si Ramu ni lilo adakọ bata

OCRAM / Ita Ramu

Bootloader nipasẹ GSFI

Nios V isise elo executein-ibi lati iṣeto ni QSPI filasi

Iṣeto ni QSPI filasi (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load () iṣẹ

Ohun elo ero isise Nios V daakọ lati iṣeto QSPI filasi si Ramu nipa lilo adakọ bata

OCRAM/ Bootloader Ramu ti ita nipasẹ GSFI tẹsiwaju…

(2) Tọkasi AN 980: Nios V Processor Quartus Prime Software Atilẹyin fun atokọ ẹrọ.

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Awọn iranti Boot atilẹyin
Iranti Lori Chip (OCRAM) Iranti Isopọpọ Ni wiwọ (TCM)

Ẹrọ
Awọn ẹrọ orisun SDM (pẹlu Onibara Apoti ifiweranṣẹ Intel FPGA IP). (2)
Gbogbo awọn ẹrọ Altera FPGA ti o ni atilẹyin (2)
Gbogbo awọn ẹrọ Altera FPGA ti o ni atilẹyin (2)

Nios V Prosessor Booting Awọn ọna
Ohun elo ero isise Nios V daakọ lati iṣeto QSPI filasi si Ramu nipa lilo adakọ bata
Ohun elo ero isise Nios V ti n ṣiṣẹ ni aaye lati OCRAM
Ohun elo ero isise Nios V ti n ṣiṣẹ ni aaye lati TCM

Ohun elo asiko isise Location

Copier bata

OCRAM / Bootloader Ramu ti ita nipasẹ SDM

OCRAM

alt_load () iṣẹ

Ilana TCM (XIP) Ko si + Data TCM (fun awọn apakan data kikọ)

olusin 28. Nios V Processor Boot Flow

Tunto

Awọn ero isise fo lati tun fekito (ibẹrẹ koodu bata)

Koodu ohun elo le ṣe daakọ si ipo iranti miiran (da lori awọn aṣayan bata)
Boot koodu initializes awọn isise

Da lori awọn aṣayan bata, koodu bata le daakọ awọn iye akọkọ fun data/koodu si aaye iranti miiran (alt_load)
Koodu bata bẹrẹ koodu ohun elo ati aaye iranti data
Koodu bata bẹrẹ gbogbo awọn agbeegbe eto pẹlu awọn awakọ HAL (alt_main)
Iwọle si akọkọ
Alaye jẹmọ · Generic Serial Flash Interface Altera FPGA IP Itọsọna olumulo
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Onibara Apoti ifiweranṣẹ Altera FPGA IP Itọsọna olumulo · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Ifihan si Nios V Processor Booting Awọn ọna
Awọn eto ero isise Nios V nilo awọn aworan sọfitiwia lati tunto ni iranti eto ṣaaju ki ero isise naa le bẹrẹ ṣiṣe eto ohun elo naa. Tọkasi Awọn apakan Linker fun awọn apakan ọna asopọ aiyipada.
Olootu BSP n ṣe agbejade iwe afọwọkọ ọna asopọ ti o ṣe awọn iṣẹ wọnyi: · Ṣe idaniloju pe sọfitiwia ero isise naa ni asopọ ni ibamu pẹlu awọn eto ọna asopọ.
ti BSP olootu ati ipinnu ibi ti software gbe ni iranti. · Awọn ipo awọn isise ká koodu ekun ni iranti paati gẹgẹ bi awọn
sọtọ iranti irinše.
Abala ti o tẹle ni ṣoki n ṣapejuwe awọn ọna gbigbe ero isise Nios V ti o wa.
4.4.1. Ohun elo Nios V Processor Execute-Ni-Place lati Boot Flash
Altera ṣe apẹrẹ awọn olutona filasi bii aaye adirẹsi filasi bata jẹ wiwọle lẹsẹkẹsẹ si ero isise Nios V lori ipilẹ eto, laisi iwulo lati bẹrẹ oluṣakoso iranti tabi awọn ẹrọ iranti. Eyi ngbanilaaye ero isise Nios V lati ṣiṣẹ koodu ohun elo ti o fipamọ sori awọn ẹrọ bata taara laisi lilo adakọ bata lati daakọ koodu si iru iranti miiran. Awọn olutona filasi ni: · On-Chip Filaṣi pẹlu On-Chip Flash IP (nikan ni MAX® 10 ẹrọ) · Gbogbogbo idi QSPI filasi pẹlu Generic Serial Flash Interface IP · Iṣeto ni QSPI filasi pẹlu Generic Serial Flash Interface IP (ayafi MAX 10
awọn ẹrọ)
Nigbati ohun elo ero isise Nios V ba ṣiṣẹ ni aaye lati filasi bata, Olootu BSP ṣe awọn iṣẹ wọnyi: · Ṣeto awọn apakan ọna asopọ ọrọ .text si agbegbe iranti filasi bata. Ṣeto awọn .bss,.rodata, .rwdata, .stack ati .heap linker awọn apakan si Ramu
agbegbe iranti. O gbọdọ mu iṣẹ alt_load () ṣiṣẹ ni Eto BSP lati daakọ awọn apakan data (.rodata, .rwdata,, .awọn imukuro) si Ramu lori ipilẹ eto. Awọn koodu apakan (.ọrọ) si maa wa ni bata filasi iranti ekun.
Alaye ti o jọmọ · Generic Serial Flash Interface Altera FPGA IP Itọsọna Olumulo · Altera MAX 10 Olumulo Filaṣi Iranti Itọsọna olumulo
4.4.1.1. alt_load()
O le mu iṣẹ alt_load () ṣiṣẹ ni koodu HAL nipa lilo Olootu BSP.
Nigbati o ba lo ni ṣiṣiṣẹ bata-ni-ibi, iṣẹ alt_load () ṣe awọn iṣẹ ṣiṣe wọnyi:

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· Ṣiṣẹ bi adakọ bata kekere ti o daakọ awọn apakan iranti si Ramu ti o da lori awọn eto BSP.
· Awọn ẹda data apakan (.rodata, .rwdata, .awọn imukuro) si Ramu ṣugbọn kii ṣe awọn apakan koodu (.ọrọ) apakan koodu (.ọrọ) apakan jẹ apakan kika-nikan ati pe o wa ni agbegbe iranti filasi booting. Pipin yii ṣe iranlọwọ lati dinku lilo Ramu ṣugbọn o le ṣe idinwo iṣẹ ṣiṣe koodu nitori awọn iraye si iranti filasi losokepupo ju awọn iraye si Ramu on-chip.

Tabili ti o tẹle yii ṣe atokọ awọn eto Olootu BSP ati awọn iṣẹ:

Table 31. BSP Editor Eto
Ṣiṣeto Olootu BSP hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Išẹ Mu iṣẹ alt_load () ṣiṣẹ. alt_load () idaako .rodata apakan to Ramu. alt_load () idaako .rwdata apakan to Ramu. alt_load () idaako .exceptions apakan to Ramu.

4.4.2. Ohun elo Nios V Processor Daakọ lati Boot Flash si Ramu Lilo Boot Copier
Awọn ero isise Nios V ati HAL pẹlu adakọ bata ti o pese iṣẹ ṣiṣe to fun pupọ julọ awọn ohun elo ero isise Nios V ati pe o rọrun lati ṣe pẹlu ṣiṣan idagbasoke sọfitiwia Nios V.
Nigbati ohun elo ba nlo adakọ bata, o ṣeto gbogbo awọn apakan asopọ (.ọrọ, .heap, .rwdata, .rodata, .bss, .stack) si Ramu inu tabi ita. Lilo aladakọ bata lati daakọ ohun elo ero isise Nios V lati filasi bata si Ramu inu tabi ita fun ipaniyan ṣe iranlọwọ lati mu ilọsiwaju iṣẹ ṣiṣe ṣiṣẹ.
Fun aṣayan bata yii, ero isise Nios V bẹrẹ sisẹ sọfitiwia idaako bata lori ipilẹ eto. Sọfitiwia naa ṣe idaako ohun elo lati filasi bata si Ramu inu tabi ita. Ni kete ti ilana naa ti pari, ero isise Nios V n gbe iṣakoso eto lọ si ohun elo naa.

Akiyesi:

Ti olupilẹṣẹ bata ba wa ni filasi, lẹhinna iṣẹ alt_load () ko nilo lati pe nitori pe awọn mejeeji ṣiṣẹ ni idi kanna.

4.4.2.1. Nios V Prosessor Bootloader nipasẹ Generic Serial Flash Interface
Bootloader nipasẹ GSFI jẹ idaako bata ero isise Nios V ti o ṣe atilẹyin iranti filasi QSPI ni awọn ẹrọ ti o da lori Àkọsílẹ iṣakoso. Bootloader nipasẹ GSFI pẹlu awọn ẹya wọnyi:
· Wa ohun elo software ni iranti ti kii ṣe iyipada.
· Unpacks ati daakọ aworan ohun elo software si Ramu.
· Yipada ipaniyan ero isise laifọwọyi si koodu ohun elo ni Ramu lẹhin ti ẹda ti pari.

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Aworan bata naa wa ni kete lẹhin ti ẹda bata. O nilo lati rii daju awọn aaye aiṣedeede atunto ero isise Nios V si ibẹrẹ ti adakọ bata. Nọmba naa: Maapu Iranti fun Flash QSPI pẹlu Bootloader nipasẹ maapu iranti GSFI fun Flash QSPI pẹlu Bootloader nipasẹ GSFI ṣe afihan maapu iranti filasi fun filasi QSPI nigba lilo adakọ bata. Maapu iranti yii dawọle iranti iranti filasi tọju aworan FPGA ati sọfitiwia ohun elo.

Table 32. Bootloader nipasẹ GSFI fun Nios V Processor mojuto

Nios V isise mojuto
Nios V / m isise

Bootloader nipasẹ GSFI File Ipo
/niosv/awọn paati/bootloader/ niosv_m_bootloader.srec

Nios V / g isise

/niosv/awọn paati/bootloader/ niosv_g_bootloader.srec

olusin 29. Memory Map fun QSPI Flash pẹlu Bootloader nipasẹ GSFI

Data Onibara (*.hex)

Koodu elo

Akiyesi:

Tun Vector aiṣedeede

Copier bata

0x01E00000

Aworan FPGA (*.sof)

0x00000000

1. Ni ibẹrẹ maapu iranti jẹ aworan FPGA ti o tẹle pẹlu data rẹ, eyiti o ni idaako bata ati koodu ohun elo.
2. O gbọdọ ṣeto aiṣedeede atunto ero isise Nios V ni Platform Designer ati tọka si ibẹrẹ ti adakọ bata.
3. Iwọn aworan FPGA jẹ aimọ.O le mọ iwọn gangan nikan lẹhin ti Quartus Prime akopo ise agbese. O gbọdọ pinnu ipinnu oke fun iwọn aworan Altera FPGA. Fun example, ti o ba ti awọn iwọn ti awọn FPGA aworan ti wa ni ifoju lati wa ni kere ju 0x01E00000, ṣeto awọn Tun aiṣedeede to 0x01E00000 ni Platform onise, ti o tun jẹ awọn ibere ti bata copier.
4. Iwa apẹrẹ ti o dara ni ti ṣeto aiṣedeede fekito atunto ni aala eka filasi lati rii daju pe ko si piparẹ apa kan ti aworan FPGA ti o ba waye ni ọran ti ohun elo sọfitiwia ti ni imudojuiwọn.

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4.4.2.2. Bootloader Processor Nios V nipasẹ oluṣakoso ẹrọ to ni aabo
Bootloader nipasẹ Oluṣakoso Ẹrọ Aabo (SDM) jẹ koodu ohun elo HAL kan ti o nlo Olubara Apoti ifiweranṣẹ Altera FPGA IP HAL awakọ fun sisọ ero isise. Altera ṣeduro ohun elo bootloader yii nigba lilo iṣeto QSPI filasi ni awọn ẹrọ orisun SDM lati bata ero isise Nios V.
Lori atunto eto, ero isise Nios V kọkọ bata Bootloader nipasẹ SDM lati inu iranti kekere lori-chip ati ṣiṣe Bootloader nipasẹ SDM lati ṣe ibasọrọ pẹlu iṣeto QSPI filasi ni lilo Onibara Apoti ifiweranṣẹ IP.
Bootloader nipasẹ SDM ṣe awọn iṣẹ ṣiṣe wọnyi: · Wa ohun elo Nios V ni filasi QSPI iṣeto ni. · Daakọ sọfitiwia Nios V sinu Ramu on-chip tabi Ramu ita. · Yipada awọn isise ipaniyan si awọn Nios V software laarin awọn on-chip Ramu tabi
Ramu ita.
Ni kete ti ilana naa ti pari, Bootloader nipasẹ SDM gbigbe eto iṣakoso lori ohun elo olumulo. Altera ṣeduro agbari iranti bi a ti ṣe ilana ni Igbimọ Iranti fun Bootloader nipasẹ SDM.
olusin 30. Bootloader nipasẹ SDM Ilana Sisan

Iṣeto ni

Filaṣi

Nios V Software

SDM

SDM-orisun FPGA Device

Onibara Apoti ifiweranṣẹ IP

FPGA Logic Nios V

4 Ramu ita
Nios V Software

Lori-Chip 4

EMIF

Àgbo

On-Chip Iranti

Nios V

Software

Bootloader nipasẹ SDM

1. Nios V isise nṣiṣẹ Bootloader nipasẹ SDM lati iranti on-chip.
2. Bootloader nipasẹ SDM ibasọrọ pẹlu awọn iṣeto ni filasi ati ki o wa awọn Nios V software.
3. Bootloader nipasẹ SDM daakọ Nios V sọfitiwia lati Filaṣi Iṣeto sinu Ramu on-chip / Ramu ita.
4. Bootloader nipasẹ SDM yipada ipaniyan ero isise Nios V si sọfitiwia Nios V ninu Ramu on-chip / Ramu ita.

4.4.3. Ohun elo Nios V Processor Execute-In-Place lati OCRAM
Ni ọna yii, adirẹsi atunto ero isise Nios V ti ṣeto si adirẹsi ipilẹ ti iranti on-chip (OCRAM). Alakomeji ohun elo (.hex) file ti wa ni ti kojọpọ sinu OCRAM nigbati FPGA ti wa ni tunto, lẹhin ti awọn hardware oniru ti wa ni compiled ninu Quartus Prime software. Ni kete ti ero isise Nios V tun bẹrẹ, ohun elo naa bẹrẹ ṣiṣe ati awọn ẹka si aaye titẹsi.

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Akiyesi:

· Execute-In-Place lati OCRAM ko nilo idaako bata nitori ohun elo ero isise Nios V ti wa tẹlẹ ni ipilẹ eto.
· Altera ṣeduro mimuuṣiṣẹ alt_load() fun ọna gbigbe yii ki sọfitiwia ti a fi sii ṣe huwa bakanna nigbati o tunto laisi atunto aworan ẹrọ FPGA naa.
O gbọdọ mu iṣẹ alt_load () ṣiṣẹ ni Eto BSP lati daakọ apakan .rwdata lori ipilẹ eto. Ni ọna yii, awọn iye akọkọ fun awọn oniyipada ipilẹṣẹ ti wa ni ipamọ lọtọ lati awọn oniyipada ti o baamu lati yago fun atunkọ lori ipaniyan eto.

4.4.4. Ohun elo Nios V Processor Execute-In-Place lati TCM
Ọna ṣiṣe-si-ibi ṣeto adirẹsi atunto ero isise Nios V si adiresi ipilẹ ti iranti so pọ mọ (TCM). Alakomeji ohun elo (.hex) file ti kojọpọ sinu TCM nigbati o ba tunto FPGA lẹhin ti o ṣajọ apẹrẹ ohun elo ni sọfitiwia Prime Quartus. Ni kete ti ero isise Nios V tun bẹrẹ, ohun elo naa bẹrẹ ṣiṣe ati awọn ẹka si aaye titẹsi.

Akiyesi:

Ṣiṣẹ-Ni-Ibi lati TCM ko nilo idaako bata nitori ohun elo ero isise Nios V ti wa tẹlẹ ni ipilẹ eto.

4.5. Nios V Processor Booting from On-Chip Flash (UFM)

Nios V isise booting ati ṣiṣe software lati on-chip filasi (UFM) wa ninu MAX 10 FPGA awọn ẹrọ. Awọn ero isise Nios V ṣe atilẹyin awọn aṣayan bata meji wọnyi ni lilo Filaṣi On-Chip labẹ Ipo Iṣeto inu:
Ohun elo ero isise Nios V ṣiṣẹ ni aaye lati Filaṣi On-Chip.
· Ohun elo ero isise Nios V ti daakọ lati Filaṣi On-Chip si Ramu ni lilo adakọ bata.

Table 33. Atilẹyin Flash Memories pẹlu oniwun Boot Aw

Awọn iranti Boot atilẹyin

Nios V Booting Awọn ọna

Ohun elo asiko isise Location

Copier bata

Awọn ohun elo MAX 10 nikan (pẹlu OnChip Flash IP)

Ohun elo ero isise Nios V ṣiṣẹ ni aaye lati Filaṣi On-Chip
Ohun elo ero isise Nios V daakọ lati On-Chip Filaṣi si Ramu ni lilo adakọ bata

Filaṣi On-Chip (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load () iṣẹ

OCRAM / Ramu ita

Tun lo Bootloader nipasẹ GSFI

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Olusin 31.

Apẹrẹ, Iṣeto ni, ati Booting Sisan
Apẹrẹ · Ṣẹda iṣẹ akanṣe orisun Nios V Processor rẹ nipa lilo Apẹrẹ Platform. · Rii daju wipe o wa ni ita Ramu tabi lori-chip Ramu ninu awọn eto oniru.

FPGA iṣeto ni ati akopo
Ṣeto ipo iṣeto inu inu kanna ni On-chip Flash IP ni Platform Designer ati Quartus Prime software. Ṣeto aṣoju atunto ero isise Nios V si Filaṣi On-chip. Yan ọna ibẹrẹ UFM ti o fẹ. · Ṣe agbekalẹ apẹrẹ rẹ ni Apẹrẹ Platform. · Ṣe akojọpọ iṣẹ akanṣe rẹ ni sọfitiwia Prime Prime.

Ohun elo olumulo BSP Project · Ṣẹda Nios V isise HAL BSP da lori .sopcinfo file da nipa Platform onise. Ṣatunkọ Nios V ero isise BSP eto ati Linker Script ni BSP Olootu. · Ṣe ipilẹṣẹ iṣẹ akanṣe BSP.
Ise agbese APP Ohun elo olumulo · Dagbasoke koodu ohun elo ero isise Nios V. Ṣe akopọ ohun elo ero isise Nios V ati ṣe ipilẹṣẹ ohun elo ero isise Nios V (.hex) file. Ṣe atunkopọ iṣẹ akanṣe rẹ ni sọfitiwia Prime Minister ti o ba ṣayẹwo Bibẹrẹ aṣayan akoonu iranti ni Intel FPGA On-Chip Flash IP.

Siseto Files Iyipada, Gbaa lati ayelujara ati Ṣiṣe · Ṣe ina Filaṣi On-Chip .pof file lilo Iyipada siseto Files ẹya-ara ni Quartus NOMBA software.
· Eto awọn .pof file sinu rẹ MAX 10 ẹrọ. · Power ọmọ rẹ hardware.
4.5.1. MAX 10 FPGA On-Chip Flash Apejuwe
Awọn ẹrọ Max 10 FPGA ni filaṣi ori-chip ti o pin si awọn ẹya meji: · Iṣeto Flash Memory (CFM) — tọju data iṣeto ni hardware fun
Iye ti o ga julọ ti 10 FPGA. Iranti Flash olumulo (UFM) - tọju data olumulo tabi awọn ohun elo sọfitiwia.
Itumọ UFM ti ẹrọ MAX 10 jẹ apapo awọn IPs rirọ ati lile. O le wọle si UFM nikan ni lilo On-Chip Flash IP Core ni sọfitiwia Quartus Prime.
On-chip Filaṣi IP mojuto ṣe atilẹyin awọn ẹya wọnyi: · Ka tabi kọ awọn iraye si UFM ati CFM (ti o ba ṣiṣẹ ni Oluṣeto Platform)
lilo Avalon MM data ati iṣakoso ẹrú ni wiwo. · Ṣe atilẹyin piparẹ oju-iwe, imukuro eka ati kikọ eka. · Awoṣe kikopa fun UFM kika / kọ awọn iraye si ni lilo ọpọlọpọ awọn irinṣẹ kikopa EDA.

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Table 34. Lori-chip Flash awọn ẹkun ni MAX 10 FPGA Devices

Awọn agbegbe Flash

Iṣẹ ṣiṣe

Iranti Filaṣi atunto (awọn apakan CFM0-2)

FPGA iṣeto ni file ibi ipamọ

Iranti Filaṣi olumulo (awọn apakan UFM0-1)

Ohun elo ero isise Nios V ati data olumulo

Awọn ẹrọ MAX 10 FPGA ṣe atilẹyin ọpọlọpọ awọn ipo atunto ati diẹ ninu awọn ipo wọnyi gba CFM1 ati CFM2 laaye lati lo bi agbegbe UFM afikun. Tabili ti o tẹle n ṣe afihan ipo ibi ipamọ ti awọn aworan iṣeto ni FPGA ti o da lori awọn ipo iṣeto MAX 10 FPGA.

Table 35. Ibi ipamọ ti awọn aworan iṣeto ni FPGA

Ipo Iṣeto ni Awọn aworan fisinuirindigbindigbin Meji

Aworan Fisinuirindigbindigbin CFM2 2

CFM1

Aworan Fisinuirindigbindigbin CFM0 1

Aworan ti ko fisinu kan

UFM foju

Aworan ti ko ni titẹ

Aworan ti a ko fikun nikan pẹlu Ibẹrẹ Iranti

Aworan ti a ko fikun (pẹlu akoonu iranti lori chip ti a ti kọkọ bẹrẹ)

Aworan fisinuirindigbindigbin ẹyọkan pẹlu Ipilẹṣẹ Iranti Aworan Fisinuirindigbindigbin (pẹlu akoonu iranti lori-ërún ti a ti kọkọ bẹrẹ)

Nikan fisinuirindigbindigbin aworan

UFM foju

Aworan Fisinu

O gbọdọ lo On-chip Flash IP mojuto lati wọle si iranti filasi ni Max 10 FPGAs. O le ese ati so On-chip Flash IP si sọfitiwia Prime Minister Quartus. Nios V asọ ti mojuto ero isise nlo Platform Designer interconnects lati baraẹnisọrọ pẹlu On-chip Flash IP.
olusin 32. Asopọ laarin On-chip Flash IP ati Nios V Processor

Akiyesi:

Rii daju pe ibudo Csr Flash On-chip ti sopọ si data_manager ero isise Nios V lati jẹ ki ero isise naa le ṣakoso kikọ ati paarẹ awọn iṣẹ rẹ.
On-chip Flash IP mojuto le pese iraye si awọn apa filasi marun - UFM0, UFM1, CFM0, CFM1, ati CFM2.
Alaye pataki nipa UFM ati awọn apa CFM .: · Awọn apa CFM jẹ ipinnu fun iṣeto (bitstream) data (* .pof) ipamọ.
· Awọn data olumulo le wa ni ipamọ ni awọn apa UFM ati pe o le farapamọ, ti o ba yan awọn eto to pe ni irinṣẹ Onise Platform.
Awọn ẹrọ kan ko ni eka UFM1 kan. O le tọka si tabili: Iwọn UFM ati CFM Sector fun awọn apa ti o wa ni ẹrọ kọọkan MAX 10 FPGA.

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· O le tunto CFM2 bi foju UFM nipa yiyan Nikan Uncompressed Image iṣeto ni mode.
· O le tunto CFM2 ati CFM1 bi a foju UFM nipa yiyan Nikan Uncompressed Image iṣeto ni mode.
Iwọn ti eka kọọkan yatọ pẹlu awọn ẹrọ MAX 10 FPGA ti a yan.

Tabili 36.

UFM ati CFM Sector Iwon
Tabili yii ṣe atokọ awọn iwọn ti awọn ọna UFM ati CFM.

Ẹrọ

Awọn oju-iwe fun Ẹka

UFM1 UFM0 CFM2 CFM1 CFM0

Iwọn oju-iwe (Kbit)

O pọju olumulo
Iwọn Iranti Filaṣi (Kbit) (3)

Lapapọ Iwọn Iṣeto Iranti (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

Iwọn OCRAM (Kbit)
108 189 378 549 675 1260 1638

Alaye ti o jọmọ · MAX 10 Itọsọna Olumulo Iṣeto ni FPGA · Altera MAX 10 Itọsọna Olumulo Iranti Filaṣi olumulo olumulo

4.5.2. Nios V Processor Application Execute-In-Place lati UFM

Ṣiṣẹ-Ni-Ibi lati ojutu UFM dara fun awọn ohun elo ero isise Nios V eyiti o nilo lilo iranti lori-chip lopin. Iṣẹ alt_load () n ṣiṣẹ bi adakọ bata kekere ti o daakọ awọn apakan data (.rodata, .rwdata, tabi .awọn imukuro) lati iranti bata si Ramu ti o da lori awọn eto BSP. Abala koodu (.ọrọ),
eyi ti o jẹ a kika nikan apakan, si maa wa ni MAX 10 Lori-chip Flash iranti ekun. Iṣeto yii dinku lilo Ramu ṣugbọn o le ṣe idinwo iṣẹ ṣiṣe koodu bi iraye si iranti filasi ti lọra ju Ramu on-chip lọ.

Ohun elo ero isise Nios V ti ṣe eto sinu eka UFM. Fekito atunto ero isise Nios V tọka si adirẹsi ipilẹ UFM lati ṣiṣẹ koodu lati UFM lẹhin awọn atunto eto naa.

Ti o ba nlo oluyipada ipele orisun lati ṣatunṣe ohun elo rẹ, o gbọdọ lo aaye fifọ ohun elo. Eyi jẹ nitori UFM ko ṣe atilẹyin iraye si iranti laileto, eyiti o jẹ pataki fun n ṣatunṣe aṣiṣe fifọ fifọ.

Akiyesi:

O ko le parẹ tabi kọ UFM lakoko ṣiṣe ṣiṣe-ni-ibi ni MAX 10. Yipada si ọna iṣagbekọ bata ti o ba nilo lati nu tabi kọ UFM naa.

(3) Awọn ti o pọju ti ṣee ṣe iye, eyi ti o jẹ ti o gbẹkẹle lori awọn iṣeto ni mode ti o yan.

Nios® V Iwe amudani Oniru ero isise 58

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olusin 33. Nios V Processor elo XIP lati UFM

Max 10 ẹrọ

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

Filaṣi On-Chip

CFM

Nios V Hardware

UFM

Nios V Software

Iṣeto inu inu

On-Chip Filaṣi IP

FPGA kannaa
Nios V isise

Lori-Chip Ramu

Ita

Àgbo

EMIF

4.5.2.1. Hardware Design Sisan
Awọn wọnyi apakan apejuwe a igbese-nipasẹ-Igbese ọna fun Ilé kan bootable eto fun ohun elo isise Nios V lati On-Chip Flash. Awọn example isalẹ wa ni itumọ ti lilo MAX 10 ẹrọ.
Awọn Eto paati IP
1. Ṣẹda iṣẹ ero isise Nios V rẹ nipa lilo Quartus Prime ati Onise Platform. 2. Rii daju Ramu ita tabi On-Chip Memory (OCRAM) ti wa ni afikun si rẹ Platform
Eto onise.

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Aworan 34. EksampAwọn isopọ IP ni Apẹrẹ Platform fun Booting Nios V lati Filaṣi OnChip (UFM)

3. Ninu oluṣatunṣe paramita IP Filaṣi On-Chip, ṣeto Ipo Iṣeto si ọkan ninu awọn atẹle, ni ibamu si ààyò apẹrẹ rẹ: · Aworan Ti a ko fisinuirindigbindigbin · Aworan Fisinuirindigbindigbin Kan · Aworan Kanṣoṣo pẹlu Ibẹrẹ Iranti · Aworan Fisinu pẹlu Ibẹrẹ Iranti
Fun alaye diẹ sii nipa Awọn aworan Fisinuirindigbindigbin Meji, tọka si Itọsọna olumulo Iṣeto MAX 10 FPGA - Igbesoke Eto Latọna jijin.

Akiyesi:

O gbọdọ fi Wiwọle pamọ si gbogbo awọn agbegbe CFM ni Filaṣi On-Chip IP.

Nọmba 35. Aṣayan Ipo Iṣeto ni On-Chip Flash Parameter Editor

Awọn Eto IP Filaṣi lori Chip – Ibẹrẹ UFM O le yan ọkan ninu awọn ọna atẹle ni ibamu si ifẹ rẹ:

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Akiyesi:

Awọn igbesẹ ti o wa ninu awọn ipin ti o tẹle (Sisan Apẹrẹ Software ati siseto) da lori yiyan ti o ṣe nibi.

· Ọna 1: Bibẹrẹ data UFM ni SOF lakoko akojọpọ
Quartus Prime pẹlu data ipilẹṣẹ UFM ninu SOF lakoko iṣakojọpọ. Atunjọpọ SOF nilo ti awọn ayipada ba wa ninu data UFM.
1. Ṣayẹwo Bibẹrẹ akoonu filasi ati Mu ipilẹṣẹ ti kii ṣe aiyipada ṣiṣẹ file.

Ṣe nọmba 36. Bibẹrẹ Awọn akoonu Filaṣi ati Mu Ibẹrẹ ti kii ṣe aiyipada ṣiṣẹ File

2. Pato ọna ti ipilẹṣẹ .hex file (lati aṣẹ elf2hex) ninu Olumulo ti o ṣẹda hex tabi mif file.
olusin 37. Fifi .hex File Ona

· Ọna 2: Darapọ data UFM pẹlu SOF ti a ṣajọpọ lakoko iran POF
Awọn data UFM ti ni idapo pẹlu SOF ti o ṣajọ nigbati o ba n yi siseto pada files. O ko nilo lati tun SOF ṣe, paapaa ti data UFM ba yipada. Lakoko idagbasoke, o ko ni lati ṣajọpọ SOF files fun ayipada ninu awọn ohun elo. Alterare ṣeduro ọna yii fun awọn olupilẹṣẹ ohun elo.
1. Ṣiṣayẹwo Bibẹrẹ akoonu filasi.
Ṣe nọmba 38. Bibẹrẹ Akoonu Filaṣi pẹlu Ibẹrẹ ti kii ṣe aiyipada File

Tunto Aṣoju Eto fun Nios V Ilana Ṣiṣe-Ni-Ipo
1. Ninu olootu paramita ero isise Nios V, ṣeto Aṣoju Tunto si Filaṣi On-Chip.
Nọmba 39. Awọn Eto Olootu Parameter Processor Nios V pẹlu Atunto Aṣoju Ṣeto si Filaṣi On-Chip

2. Tẹ Ina HDL nigbati awọn Iran apoti ajọṣọ han. 3. Pato o wu file iran awọn aṣayan ki o si tẹ Ina.

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Awọn Eto Software Quartus Prime 1. Ninu sọfitiwia Quartus Prime, tẹ Ẹrọ Awọn iṣẹ iyansilẹ ati PIN
Iṣeto Awọn aṣayan. Ṣeto ipo Iṣeto ni ibamu si eto ni Filaṣi On-Chip IP. Ṣe nọmba 40. Aṣayan Ipo Iṣeto ni Quartus Prime Software

2. Tẹ O dara lati jade ni Device ati Pin Aw window,
3. Tẹ O DARA lati jade ni Device window.
4. Tẹ Ṣiṣe Ibẹrẹ Ibẹrẹ lati ṣajọ iṣẹ rẹ ati ṣe ina .sof file.

Akiyesi:

Ti ipo iṣeto ni Quartus Prime sọfitiwia ati olootu paramita Apẹrẹ Platform yatọ, iṣẹ akanṣe Quartus Prime kuna pẹlu ifiranṣẹ aṣiṣe atẹle.

Olusin 41.

Ifiranṣẹ aṣiṣe fun Aṣiṣe Iṣeto Iṣeto Oriṣiriṣi (14740): Ipo iṣeto ni atom "q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block ise agbese. ko baramu. Ṣe imudojuiwọn ati ṣe atunto eto Qsys lati baamu eto iṣẹ akanṣe.

Alaye ti o jọmọ MAX 10 Itọsọna olumulo Iṣeto FPGA

4.5.2.2. Software Design Sisan
Abala yii n pese ṣiṣan apẹrẹ lati ṣe ipilẹṣẹ ati kọ iṣẹ sọfitiwia ero isise Nios V. Lati rii daju ṣiṣan kikọ ṣiṣanwọle, o gba ọ niyanju lati ṣẹda igi ilana ti o jọra ninu iṣẹ akanṣe rẹ. Ṣiṣan apẹrẹ sọfitiwia atẹle yii da lori igi liana yii.
Lati ṣẹda awọn software ise agbese liana igi, tẹle awọn igbesẹ: 1. Ninu rẹ oniru ise agbese folda, ṣẹda a folda ti a npe ni software. 2. Ninu folda software, ṣẹda awọn folda meji ti a npe ni hal_app ati hal_bsp.
olusin 42. Software Project Directory Tree

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Ṣiṣẹda Ohun elo BSP Project
Lati ṣe ifilọlẹ Olootu BSP, tẹle awọn igbesẹ wọnyi: 1. Tẹ Nios V Command Shell sii. 2. Pe Olootu BSP pẹlu aṣẹ niosv-bsp-editor. 3. Ni BSP Olootu, tẹ File BSP tuntun lati bẹrẹ iṣẹ akanṣe BSP rẹ. 4. Tunto awọn eto wọnyi:
· SOPC Alaye File orukọ: Pese SOPINFO file (.sopcinfo). · Sipiyu orukọ: Yan Nios V isise. · Eto iṣẹ: Yan ẹrọ iṣẹ ti ero isise Nios V. · Ẹya: Fi silẹ bi aiyipada. · Ilana ibi-afẹde BSP: Yan ọna itọsọna ti iṣẹ akanṣe BSP. O le
kọkọ-ṣeto ni /software/hal_bsp nipa muu ṣiṣẹ Lo awọn ipo aiyipada. · BSP Eto File orukọ: Tẹ awọn orukọ ti awọn BSP Eto File. · Awọn iwe afọwọkọ Tcl ni afikun: Pese iwe afọwọkọ BSP Tcl nipa mimuu ṣiṣẹ ni afikun iwe afọwọkọ Tcl. 5. Tẹ O DARA.
olusin 43. Tunto New BSP

Ṣiṣeto Olootu BSP ati Ṣiṣẹda Ise agbese BSP
O le setumo fekito imukuro ero isise boya ni On-Chip Memory (OCRAM) tabi Filaṣi On-Chip ti o da lori yiyan apẹrẹ rẹ. Ṣiṣeto iranti iranti imukuro iyasọtọ si OCRAM/Ramu ita ni a gbaniyanju lati jẹ ki sisẹ idalọwọduro ni iyara. 1. Lọ si akọkọ Eto To ti ni ilọsiwaju hal.linker. 2. Ti o ba yan Filaṣi On-Chip gẹgẹbi iyatọ ti o yatọ,
a. Mu awọn eto atẹle ṣiṣẹ:

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· allow_code_at_reset · sise_alt_load · sise_alt_load_copy_rodata · sise_alt_load_copy_rwdata Nọmba 44. Advanced.hal.linker Eto

b. Tẹ lori taabu Afọwọkọ Linker ni Olootu BSP. c. Ṣeto awọn .awọn imukuro ati awọn agbegbe .text ni Orukọ Abala Linker si
Filaṣi On-Chip. d. Ṣeto awọn iyokù ti awọn agbegbe ni Akojọ Orukọ Abala Linker si On-Chip
Iranti (OCRAM) tabi Ramu ita.
Ṣe nọmba 45. Awọn Eto Agbegbe Linker (Iyatọ Iranti Vector: Filaṣi On-Chip)

3. Ti o ba yan OCRAM / Ita Ramu bi sile fekito, a. Mu eto wọnyi ṣiṣẹ: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · sise_alt_load_copy_rwdata · sise_alt_load_copy_exception
Nọmba 46. Awọn Eto Agbegbe Linker (Iyasọtọ Vector Memory: OCRAM/Ramu Ita)

b. Tẹ lori taabu Afọwọkọ Linker ni Olootu BSP.
c. Ṣeto awọn agbegbe.text ni Orukọ Abala Linker si Filaṣi On-Chip.
d. Ṣeto awọn agbegbe to ku ni atokọ Orukọ Abala Linker si Iranti On-Chip (OCRAM) tabi Ramu ita.

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Nọmba 47. Awọn Eto Agbegbe Linker (Iyasọtọ Vector Memory: OCRAM)
4. Tẹ Ina lati se ina ise agbese BSP. Ti o npese awọn User elo Project File 1. Lilö kiri si software/hal_app folda ki o si ṣẹda rẹ elo orisun
koodu. 2. Lọlẹ Nios V Command Shell. 3. Ṣiṣe pipaṣẹ ni isalẹ lati ṣe ina ohun elo CMekeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/
Ṣiṣe Ise agbese Ohun elo Olumulo O le yan lati kọ iṣẹ akanṣe ohun elo olumulo nipa lilo Ashling RiscFree IDE fun Altera FPGA tabi nipasẹ wiwo laini aṣẹ (CLI). Ti o ba fẹran lilo CLI, o le kọ ohun elo olumulo nipa lilo aṣẹ atẹle: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/kọ
Ohun elo naa (.elf) file ti ṣẹda ni software / hal_app / folda kọ. Ṣiṣẹda HEX File O gbọdọ ṣe ina .hex file lati rẹ elo .elf file, ki o le ṣẹda kan .pof file o dara fun siseto awọn ẹrọ. 1. Lọlẹ Nios V Command Shell. 2. Fun Nios V isise ohun elo bata lati On-Chip Flash, lo awọn wọnyi
Laini aṣẹ lati yi ELF pada si HEX fun ohun elo rẹ. Aṣẹ yii ṣẹda ohun elo olumulo (onchip_flash.hex) file. sọfitiwia elf2hex/hal_app/build/ .elf -o onchip_flash.hex
-b w 8-e 3. Ṣe atunto apẹrẹ hardware ti o ba ṣayẹwo Initialize akoonu akoonu iranti ni On-Chip Flash IP (Ọna 1). Eyi ni lati ṣafikun data sọfitiwia (.HEX) ninu SOF file.

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4.5.2.3. Siseto 1. Ni Quartus Prime, tẹ File Yipada siseto Files. 2. Labẹ o wu siseto file, yan Ohun pirogirama File (.pof) bi siseto file iru. 3. Ṣeto Ipo si Ti abẹnu iṣeto ni.
olusin 48. Iyipada siseto File Eto
4. Tẹ Aw/Bata info…, awọn Max 10 Device Aw window han. 5. Da lori Initialize filasi akoonu eto ni On-chip Flash IP, ṣe
Ọkan ninu awọn igbesẹ wọnyi: · Ti a ba ṣayẹwo akoonu filasi Initialize (Ọna 1), data ipilẹṣẹ UFM
wa ninu SOF lakoko ikojọpọ Quartus Prime. - Yan Page_0 fun orisun UFM: aṣayan. Tẹ O DARA ki o tẹsiwaju si
Itele. Nọmba 49. Ṣiṣeto Oju-iwe_0 fun Orisun UFM ti o ba ti ṣe ayẹwo Akoonu Filaṣi bẹrẹ

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Ti ko ba ṣayẹwo akoonu filasi pilẹ (Ọna 2), yan iranti fifuye file fun aṣayan orisun UFM. Lọ kiri lori ayelujara si ti ipilẹṣẹ On-chip Flash HEX file (onchip_flash.hex) ninu awọn File ona: ki o si tẹ O dara. Igbese yii ṣafikun data UFM lọtọ si SOF file nigba siseto file iyipada.
olusin 50. Eto Fifuye Memory File fun Orisun UFM ti a ko ba Ṣayẹwo akoonu Filaṣi bẹrẹ

6. Ni awọn Iyipada siseto File apoti ajọṣọ, ni Input files lati se iyipada apakan, tẹ Fikun-un File… ati tọka si Quartus Prime .sof ti ipilẹṣẹ file.
olusin 51. Input Files lati Iyipada ni Iyipada siseto Files fun Nikan Aworan Ipo

7. Tẹ Ina lati ṣẹda awọn .pof file. 8. Eto awọn .pof file sinu rẹ MAX 10 ẹrọ. 9. Power ọmọ rẹ hardware.

4.5.3. Ohun elo Nios V Processor Daakọ lati UFM si Ramu ni lilo Boot Copier

Altera ṣe iṣeduro ojutu yii fun MAX 10 FPGA Nios V awọn apẹrẹ eto ero isise nibiti ọpọlọpọ awọn iterations ti idagbasoke sọfitiwia ohun elo ati iṣẹ ṣiṣe eto giga nilo. Oludaakọ bata wa laarin UFM ni aiṣedeede ti o jẹ adirẹsi kanna bi fekito atunto. Ohun elo Nios V wa ni atẹle si adakọ bata.

Fun aṣayan bata yii, ero isise Nios V bẹrẹ ṣiṣe adaṣe bata lori ipilẹ eto lati daakọ ohun elo lati eka UFM si OCRAM tabi Ramu ita. Ni kete ti didakọ ti pari, ero isise Nios V n gbe iṣakoso eto lọ si ohun elo naa.

Akiyesi:

Oludaakọ bata ti a lo jẹ kanna bii Bootloader nipasẹ GSFI.

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Nios® V Iwe amudani Oniru ero isise 67

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olusin 52. Nios V Ohun elo Daakọ lati UFM to Ramu lilo Boot Copier

Max 10 ẹrọ

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

Ramu ita
Nios V Software

Filaṣi On-Chip

CFM

Nios V Hardwa

Awọn iwe aṣẹ / Awọn orisun

Nios V Ifibọ Prosessor

User Guide · Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

Awọn itọkasi

Itọsọna olumulomanual.tools

Published: September 6, 2025

Imudojuiwọn: Oṣu Kẹsan Ọjọ 9, Ọdun 2025

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Awọn iwe aṣẹ / Awọn orisun

Awọn itọkasi

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